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  1. #1
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    MachXO2 and SFP transceiver data issues

    Hello all!

    I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs connected to a SFP modules and using single mode fiber cable.

    I'm using Lattice's MACHXO2 LCMXO2-1200HC-6TG144C model. The DDR interfaces work with clocks of 125 MHz, for transmitter it will send data at 250 MHz and for receiver it uses phase shift on the 125 MHz to sample the data. The transmitter uses the same clock of the system (125 MHz) and the receiver has a dedicated clock of 125 MHz. The signal that sends by optical fiber is a FSK signal where when sending two zeros or two ones followed activates the trigger condition. Exactly, data strings are sent like the following 0101010011010101 ... All these data after being read by the DDR receiver pass to a shifter register on which the detection algorithm is carried out.

    In the simulations the detection algorithm works well and after testing it in PCB the following happens:

    - Connecting the TX transmitter of the SFP transceiver to the RX port of the same transceiver (on same board), the algorithm seems to work and it correctly detects the signal sending indicator pattern, arriving at distances up to 15 km of optical fiber.
    - On the other hand, if I connect the TX transmitter of an SFP transceiver to the RX port of another transceiver of another PCB board, the system jumps its trigger condition continuously, even sending only the succession of zeros and ones unmodified.

    The DDR interfaces have been created using the Lattice IP editor, and both the TX transmission line and the RX receive line have resistors that adapt the signal to LCPECL interface.

    I would like to know where to begin to address the problem.

    Thank you very much and greetings.

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  2. #2
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    Re: MachXO2 and SFP transceiver data issues

    Hi,

    The transmitter uses the same clock of the system (125 MHz)
    A simulator may treat two "independent" 125MHz clocks as synchronous clocks.
    But in reality every clock source has itīs own frequency tolerance, frequency drift and jitter.

    There need to be some synchronisation technique.

    ****
    Show us a schematic/draft where we can see transmitters, recievers, FPGAs, clock generators, fiber cable...
    Give them unique names, so we can refer to them for further discussion.

    Klaus
    Please donīt contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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  3. #3
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    Re: MachXO2 and SFP transceiver data issues

    Quote Originally Posted by KlausST View Post
    A simulator may treat two "independent" 125MHz clocks as synchronous clocks.
    But in reality every clock source has itīs own frequency tolerance, frequency drift and jitter.
    Klaus
    This was the first thing that came to mind. You'll likely need to recover the clock from the RX data.



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