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  1. #1
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    simulation problem in verilog

    I have coded following verilog code for getting e to the power x. but I am getting only integers. I want answer in real number.How to get it.

    Code Verilog - [expand]
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    //Expo program
    //Expo program
    module expo(power,ans,acc);
      input [7:0]power;
      input [7:0]acc;
      output [15:0]ans;
      real [15:0]anstemp;
      real [15:0]temp;
      real [7:0]i; 
     
      always@*
      begin
     
    anstemp=1;
    temp=1;
     
        for(i=1;i<=acc;i=i+1)
        begin 
          temp=(temp*power)/i; 
    anstemp=anstemp+temp;
        end
      end
     
    assign ans=anstemp;
    endmodule
     
    its testbench is as follows.
     
    module expotb;
      reg [7:0]power;
      reg [7:0]acc;
      wire [15:0]ans;
     
      expo A1(power,ans,acc);
     
    initial
    begin 
     
    power=5;
    acc=10000;
    end
     
    always @(ans)
      $display( "time =%0t \t output value ans  =%d  ",$time,ans);
    endmodule

    •   Alt11th May 2018, 13:06

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  2. #2
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    Re: simulation problem in verilog

    Quote Originally Posted by NEHA12345 View Post
    I have coded following verilog code for getting e to the power x. but I am getting only integers. I want answer in real number.How to get it.

    Code Verilog - [expand]
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    //Expo program
    //Expo program
    module expo(power,ans,acc);
      input [7:0]power;
      input [7:0]acc;
      output [15:0]ans;
      real [15:0]anstemp;
      real [15:0]temp;
      real [7:0]i; 
     
      always@*
      begin
     
    anstemp=1;
    temp=1;
     
        for(i=1;i<=acc;i=i+1)
        begin 
          temp=(temp*power)/i; 
    anstemp=anstemp+temp;
        end
      end
     
    assign ans=anstemp;
    endmodule
     
    its testbench is as follows.
     
    module expotb;
      reg [7:0]power;
      reg [7:0]acc;
      wire [15:0]ans;
     
      expo A1(power,ans,acc);
     
    initial
    begin 
     
    power=5;
    acc=10000;
    end
     
    always @(ans)
      $display( "time =%0t \t output value ans  =%d  ",$time,ans);
    endmodule
    As there is no intention of synthesizing the design (you are writing a program) I would drop using Verilog and do with this in C/C++.

    If the intention is to put this on an FPGA the everything you are doing is wrong.
    No clock: always @*
    for loop programming
    real numbers

    Verilog is a Hardware Description Language so you are supposed to descripe a digital circuit], not write a software programs.



    •   Alt11th May 2018, 14:23

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  3. #3
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    Re: simulation problem in verilog

    The test bench receives an integer number and displays it using an integer format. Where do you expect a real value?

    I wonder which simulator accepts the shown Verilog program. Real is an abstract data type to be used in simulation only and has no bit length. Respectively a declaration like below make no sense.
    Code:
    real [15:0]anstemp;



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