nanochick2011
Newbie level 1
Hello all,
I am simulating a Type-I PLL, and here is my question about Type-I PLL.
I do know that a Type-I PLL can easily adopt XOR as PD,
but PD's characteristic of phase error and averaged Vout is "periodic", as the figure below.
We can only use the linear and positive slope region, which is from 0 to pi.
But in normal PLL operation, we can not promise that the phase error always remain in 0 to pi.
and the loop may be unstable if the phase error is outside the range.
So, I am curious about how it works.
Is there additional subcircuit that limit the phase error within 0 to pi?
Thanks.
I am simulating a Type-I PLL, and here is my question about Type-I PLL.
I do know that a Type-I PLL can easily adopt XOR as PD,
but PD's characteristic of phase error and averaged Vout is "periodic", as the figure below.
We can only use the linear and positive slope region, which is from 0 to pi.
But in normal PLL operation, we can not promise that the phase error always remain in 0 to pi.
and the loop may be unstable if the phase error is outside the range.
So, I am curious about how it works.
Is there additional subcircuit that limit the phase error within 0 to pi?
Thanks.