# Numerical computation in FPGA

1. ## Numerical computation in FPGA

Currently I am interfacing FPGA to ADC and the ADC outputs 0-4095 counts corresponding to 0-5V. In FPGA I would like to convert these counts back to process value. What are the methods to achieve this objective?

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2. ## Re: Numerical computation in FPGA

What do you mean by convert the counts back?

The outputs of the ADC represent the input voltages seen on the analog input of the ADC. i.e. 0V == 0, 2.5V== 2047, and 5V == 4095, and all other values (counts) between represent other voltages.

3. ## Re: Numerical computation in FPGA

4095 counts have to be translated to process value just like we do with micro-controllers. I have to do numerical scaling ( to convert the count to physical value to indicate pressure, temperature etc) of the count value and then display in LCD or 7 segment LED.

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4. ## Re: Numerical computation in FPGA

Hi,

Why these vague informations?

Example for a 3 digit voltmeter:
0...4095 (ADC) --> "0.00" ... "5.00"

This means 500 steps with a value of 10mV per step on the display.
The according decimal point in the display simple is fixed "ON" and has nothing to do with the calculation.
The solution to the above is to multiply the ADC_value with 500/4096.
Do this as an integer multiplication with the value 500. At least 12bits x 9 bits = 21 bits. Ignore the lower 12 bits of the result.

Klaus

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5. ## Re: Numerical computation in FPGA

Hi

Can we just use the divide function (say in verilog) as you have proposed or should we customize the division function?

6. ## Re: Numerical computation in FPGA

As ads-ee mentioned, the 12 bit unsigned number represents already the process value and don't necessarily need to be converted. Conversion to engineering units with defined scaling is however a possible operation, for example integer millibar or 0.1 °C, also gain and zero adjustment ("calibration") of measurement values. If you start with practical FPGA coding, you'll realize that division by a constant factor is a bad idea due to large resource consumption of the divider unit. Instead you'll use fixed point multiply.

7. ## Re: Numerical computation in FPGA

Hi FvM

Thanks for that info. I finally understood the concept. I am really looking for a hardware efficient multiplier algorithm to be implemented in verilog.

8. ## Re: Numerical computation in FPGA

Modern FPGA synthesis tools almost free you from worrying about efficient multiplier algorithms. It's your job to design the dataflow and useful pipelining for everdays numerical computation problems.

9. ## Re: Numerical computation in FPGA

I don't think this is a good use-case for a multiplier. The problem is to display a value in decimal format. For this, a small FSM with an adder/subtractor seems correct. The FSM would accumulate 100 (just a guess) samples. After getting 100 samples, the fsm would try to subtract 1V. if there are 4095 counts per 5V, then there 819 counts per 1V. Because the samples have been accumulated 100 times, 1V would be 81900 in the accumulated version. With each subtraction, the unit place of a temporary output value is incremented. this continues until the accumulator is lower than 81900. At that point, 8190 is subtracted until accumulator is less than 8190. the 0.1's place is determined based on the number of times 8190 is subtracted. The process repeats for 819 to get the .01's place. After this, the temporary output value is moved to the output -- all digits update at the same time.

There are other variations on this. This one is easy to understand. The sampling rate should make it clear if accumulating 100 samples is acceptable, or if the input should be multiplied by 10 or 100.

10. ## Re: Numerical computation in FPGA

Hi,

Yes, this is the overall ADC to Display (BCD) solution.

The multiply solution is a general solution like asked in post#1.
(In post#1 here is no BCD and no display)

Indeed for ADC to Display I'd prefer a microcontroller.
It's easier to do offset and gain calibration and store the calibration values in EEPROM.
Interrupt driven it may just take 1% of processing power.

Klaus

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11. ## Re: Numerical computation in FPGA

Originally Posted by gary36
Hi FvM

Thanks for that info. I finally understood the concept. I am really looking for a hardware efficient multiplier algorithm to be implemented in verilog.
Hello,

almost all of modern FPGAs have hardware multipliers "on board".