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Noise in CMOS Inverter

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With the RC approach, you get a slightly different value, but also the DC point has shifted a bit.

I am bit worried about the shift in DC point at the input.

If the purpose is just to make Vout ~= Vin of the inverter for constant DC operating point and eliminates any feedback in AC, why not just use a very LARGE inductor between input and output since impedance of inductor = jwL ? This also eliminates the need of an input AC-shunt capacitor.
 
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This also eliminates the need of an input AC-shunt capacitor.
Sounds like you have forgotten the thread questions in the meantime. The problem was to measure output impedance. You necessarily need to ground the amplifier input AC-wise to get the output impedance. Using only an "infinite" inductance for DC feedback leaves the input floating.
 

@FvM

wait, I suppose for AC analysis, simulator will "short" the DC input voltage source to AC ground ? if yes, then we do not need any AC shunt capacitor at the input of CMOS inverter.

Please correct me if I am wrong
 

Which simulation circuit are you talking about? The input can be either biased with a DC source, or a DC feedback circuit. Using a DC feedback circuit (RC, inductor, whatsoever) makes only sense if there's no DC voltage source. See explanation in post # 14.
 

I am bit worried about the shift in DC point at the input.

I think that's due to the leakage current of the gates in this transistor model. The shift is very small and the R_out result did not change much. In dB it's miniscule... and variations due to mismatch or what-have-you would be much larger.
 

@jjx

Sorry for taking up your time for some more theory before the actual simulation

The screenshot is taken from **broken link removed**

1) On slide 17, how do we derive the Vih and Vil expressions involving the variable 'g' which I suppose is total gm of the CMOS inverter ?

2) On slide 19, how do we derive the gain determinates function for the saturation condition Vin=Vm ?


zi10j65.png
 

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Hi,

no worries.

1) A bit cryptic slide... g is the voltage gain not the transconductance. Given the diagram and what they mention in the first sentence they assume g = -1 and a PWL function. That gives you the straight lines and the VOL = 0 and VOH = VDD, and VM = (VOH+VOL)/2 = (VDD - 0)/2 = VDD/2

2) Haven't really looked into the details, but it should be possible to derive directly from something like:

g = (gmp + gmn) / (gdsp + gdsn) = (2 ID / Veffp + 2 ID / Veffn) / ( lambdaP ID + lambdaN ID) = (1 / (VDD-VM-VTP) + 1 / ( VM - VTN) ) / ( ( lambdaP + lambdaN) / 2) = (VM - VTN + VDD - VM - VTP ) / ( (VDD-VM-VTP) * ( VM - VTN) * ( lambdaP + lambdaN) / 2) = ( VDD - VTN - VTP ) / ( (VDD - VM - VTP) * ( VM - VTN) * ( lambdaP + lambdaN) / 2) etc.

In this case, I think they have made some assumptions, that the gm of the N and P are equal, and that the r factor might be some correction factor for that. I you do those assumptions, one can land at something like the expression above.
 
@jjx

See **broken link removed** for the derivation steps

But I do not understand why Vih = Vm - Vm / g
 

Ok, so their formulae motivates the max g quite well. (Even though I still don't see the definition of r)

For Vih = Vm - Vm/g

That comes from the linearized transfer curve around the operating point (VIN = VOUT = VM)

vOUT = VOUT + Dvin * dvout/dvin = VOUT + Dvin * g

where

vIN = VIN + Dvin

When

vIN = VIN + Dvin = VM + DVin = VIH => Dvin = VIH - VM

Such that

vOUT(vIN=VIH) = VM + (VIH - VM) * g = 0 => (VIH - VM)*g = -VM => VIH = VM - VM/g
 

vIN = VIN + Dvin

wait, why do you have vIN and VIN ?

and what is the difference between vOUT and VOUT ?

- - - Updated - - -

I got it now. See the following derivation for Vih

TsiyMQC.png


CMOS_Inverter_noise_margin.png
 

r = kp*Vdsatp / kn*Vdsatn

@jjx

What do you think about r as someone helped me to defined what r actually refers to ?

But, (Vm - Vth - Vdsatn/2) does not seem to imply saturation condition when Vin = Vm ?
 
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Ok, thanks. Makes sense given the set of equations that you provided in the link before.
 

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