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Noise in CMOS Inverter

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promach

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For **broken link removed** ,


1) Why would CMOS inverter performs poorly in terms of supply noise rejection ratio ? Could anyone explain maths equations ?

2) Could anyone elaborate on this statement "The output resistance is a good measure of the sensitivity of the gate in respect to noise induced at the output, and is preferably as low as possible" ?

3) Could anyone suggest a good circuit methodology to measure the output resistance of CMOS inverter ?
 

1, From small signal, small frequency model: Vout/Vsupply = (gmP + gdsP) / (gdsN + gdsP). So it gains supply noise not rejects.
2, If a load can pull away the output of the inverter's voltage it is better if the output resistance is low as possible. I think it want to say that.
3, Output resistance of an inverter is 1/(gdsP + gdsN) at small frequencies. You can get these from DC oppoint simulation.
 

I presume you are analyzing the inverter in linear mode, with both transistors in saturation. The output current is the sum of NMOS and PMOS drain current then. For the shorted case Rload << Rout you get

Code: 
dIout = -dVin*(gmNMOS + gmPMOS) - dVdd*gmPMOS

Means the PMOS transistor generates a strong power supply effect, without considering output resistance at all. Statement 2 is in so far misleading I think.
 

An addition to 3 could be:

Sweep the input DC level and perform an AC analysis for each DC level. Inject a 1A current into the output and measure the AC voltage output at say 1 Hz as the output resistance.
 

@frankrose

Vout/Vsupply = (gmP + gdsP) / (gdsN + gdsP).
Click to expand...

This looks like Vout/Vin instead of Vout/Vsupply to me
 

promach, look it from closer. Vout/Vin is (gmP + gmN) / (gdsP + gdsN), that else. And both equations have boundaries.
 

@frankrose

My small signal circuit analysis skill is still very poor. Could you show us how to derive Vout/Vsupply = (gmP + gdsP) / (gdsN + gdsP) ?
 

<a href="https://imgur.com/C4QjRif"><img src="https://i.imgur.com/C4QjRifm.png" title="source: imgur.com" /></a>
 
FvM said:
I presume you are analyzing the inverter in linear mode, with both transistors in saturation. The output current is the sum of NMOS and PMOS drain current then. For the shorted case Rload << Rout you get

Code: 
dIout = -dVin*(gmNMOS + gmPMOS) - dVdd*gmPMOS

Means the PMOS transistor generates a strong power supply effect, without considering output resistance at all. Statement 2 is in so far misleading I think.
Click to expand...

@FvM

How do you obtain the extra term "dVdd*gmPMOS" ?

- - - Updated - - -

@frankrose

Which method (DC op point simulation / AC analysis) is more suitable in output impedance measurement of any circuit (not just CMOS inverter) ?
 

How do you obtain the extra term "dVdd*gmPMOS" ?
Click to expand...
frankrose has elaborated about it in the meantime. It's the same as Vsupply*gmP in the post #8 scheme. As mentioned before, this term is actually the dominant one in poor inverter power supply rejection.
Which method (DC op point simulation / AC analysis) is more suitable in output impedance measurement of any circuit (not just CMOS inverter) ?
Click to expand...
AC analysis basically, but AC analysis of a non-linear circuit depends on a correct DC operation point.
 

@FvM

Could you suggest/sketch a suitable test circuit for output impedance measurement in AC analysis domain ? What kind of load elements do I need ?
 

A setup has been suggested in post #4. You'll find a way to bias the inverter in the intended operation point, e.g. Vout = Vdd/2.
 

Sweep the input DC level and perform an AC analysis for each DC level.
Click to expand...

why sweep DC level and then for each DC level, perform AC analysis ?
 

The AC analysis is a linearization of the DC operating point. The inverter is very sensitive to its operating point.

The AC analysis will give you quite different response if you are operating at cut-off or in the transition region. In your case, while discussing noise, the inverter is indeed most sensitive to noise in the transition region.

With the DC analysis find the trip-point, where the output voltage is set at VDD/2, perform the AC analysis. The current source, injecting current into the output, should be a 1-A AC.

You could also use a feedback in the simulator to set the output to vdd/2. That could be used to omit the DC sweep to find the trip point.
 
For **broken link removed** , why both the capacitance have to be large ?

The Rbias has to be large as well, right ? Vgs set to Vdd/2 ?
 

Each capacitance should be large compared to the connected node impedance. If you are underemployed, you can calculate how large exactly, or just make it very "large" in the simulation.

The Rbias has to be large as well
Click to expand...
Yes.

Vgs set to Vdd/2 ?
Click to expand...
The inverter is self biased, don't set Vgs manually.
 

Each capacitance should be large compared to the connected node impedance.
Click to expand...

Would you mind elaborating on the above quote ?
 

The capacitors must be large such that they can be ignored from the calculation. I do not think you need to add the external C_large though (on the output). If you do not use the C_large at the input, you get somewhat strange results. You want to AC-shunt the input to ground quite quickly in the frequency domain, such that the resistance can be ignored.

However, trying out is probably best. In cadence, you can use a switch to set the DC point at the input based on the output such that they are more or less the same. Then run the AC analysis.

With the RC approach, you get a slightly different value, but also the DC point has shifted a bit.

Capture2.PNG
Capture3.PNG
 

use a switch to set the DC point at the input based on the output such that they are more or less the same
Click to expand...

What ? Why use switch ? and how does this make the output and intput "more or less" the same ?

- - - Updated - - -

I understand what you mean by switch now.

As in the second picture, you have a resistor connected between the input and output. But what about the two green AC response waveforms at the right ? Could you briefly describe AC response ?

- - - Updated - - -

If you do not use the C_large at the input, you get somewhat strange results. You want to AC-shunt the input to ground quite quickly in the frequency domain, such that the resistance can be ignored.
Click to expand...

@jjx ignore resistance ? which resistance were you referring to exactly ?

by the way, in the case of output impedance measurement, do we still need the C_large at the input ? and why ?
 

"ignore resistance" -- sorry, my bad English. The capacitor will ground the input for higher frequencies (actually from quite low frequencies if the capacitor is laaaaarge). Thereby, the resistor will not feedback any of the output to the input.

The two green curves. The upper one is a simulation without the capacitor. The lower one with a capacitor showing a more correct result.
 

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