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BJT based PTAT architecture

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ashrafsazid

ashrafsazid

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Hi,

I would like to know if there are more possibilities available apart from the simple PTAT generator using two BJTs and feeding them a current of a certain ratio (depending on the sensitivity). Is there any other possible architectures using parasitic BJTs in CMOS technology?

Thanks.
 

Parasitic BJTs usually have the collector pinned to sub!
and you only have the emitter & base free to play with.
So you need something else to make the gain needed.

If you have a twin-well CMOS then you can get real
3-terminal / 4-terminal BJTs and make simpler PTATs
(you can do it with 2 NPN, 2 PNP, 1 resistor excluding
startup considerations). Of course BJTs made from
CMOS wells are generally quite lousy and you need
over-unity gain around the loop at low current. A
diode-connected (C=B) parasitic BJT, you don't really
care about beta. Just stuff current down it and play
with the ratios.
 

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