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    Verilog: declaring variable as reg throws an error

    Code:
    module multiplier(
        input clk,
        input [15:0] a,
        input [15:0] b,
        output reg [31:0] p
        );
        
    reg [31:0] in;
    
    always@(posedge clk) begin
    
    p  <= a*b*in;
    in <= in+1;
    
    end  
    multi_test mu(
        .clk(clk),
        .in(in[15:0])
        );     
        
    endmodule
    hi above is a demo for my problem,,,,"in" output of multi_test , i must used in two places like above (its demo).. but when i synthesize it , its throwing an error "in" must be a wire. but if i declare it as a wire i cant use it inside always block.

    how to solve this?
    did anybody came across this issue before ,any help is really appreciated
    how to assign the value of wire to a reg?
    UPDATE ..............................................
    now i am doing like below
    Code:
        reg [31:0] in2;
      
      always@(posedge clk) begin
      in2 =in;
      end
    any other way ?

    thanks and regards
    Last edited by andre_teprom; 9th May 2018 at 11:18. Reason: title descriptive

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    Re: Verilog: declaring variable as reg throws an error

    throwing an error "in" must be a wire
    Can't reproduce the error. It makes no sense IMHO.



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    Re: Verilog: declaring variable as reg throws an error

    Seems like you are confused between Verilog register and wire types.

    p <= a*b*in;
    I think a and b default to wire types since they are not explicitly defined as reg. However your output p is of type reg.
    In the operation shown above you are mixing the types.

    how to assign the value of wire to a reg?
    Register your inputs a and b on the rising edge of the clk, then use that value to do whatever operation you want to.
    FPGA enthusiast!



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    Re: Verilog: declaring variable as reg throws an error

    Of course in of multi_test can't be an output, gives multiple drivers for variable in.



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    Re: Verilog: declaring variable as reg throws an error

    sorry for my bad explanation::
    module multiplier(
    input clk,
    input [15:0] a,
    input [15:0] b,
    output reg [31:0] p
    );


    reg [31:0] in;

    always@(posedge clk) begin

    p <= a*b*in;
    in <= in;

    end
    multi_test mu(
    .clk(clk),
    .in(in[15:0])
    );

    endmodule
    here i am getting error
    [Synth 8-685] variable 'in' should not be used in output port connection ["/home/dipin/development/multi_test/multi_test/multi_test.srcs/sources_1/new/multiplier.v":41]
    above is not my exact code...its a demo....so how can i use " in " value inside always block for some operations like above

    thanks



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    Re: Verilog: declaring variable as reg throws an error

    I understand that you want the data flow as below
    Code Verilog - [expand]
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    module multiplier(
        input clk,
        input [15:0] a,
        input [15:0] b,
        output reg [31:0] p
        );
        
    reg [31:0] in2;
    wire [15:0] in;
     
    always@(posedge clk) begin
    p  <= a*b*in2;
    in2 <= in+1;
    end  
    multi_test mu(
        .clk(clk),
        .i_am_output(in[15:0])
        );     
    endmodule
    "in" must be declared as wire in Verilog2001, can be reg with SystemVerilog syntax enabled.

    Btw., anything against using meaningful variable names?


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    Re: Verilog: declaring variable as reg throws an error

    HI,
    Thanks for the help FvM,
    Btw., anything against using meaningful variable names?
    Sorry next time i will do it..
    module multiplier(
    input clk,
    input [15:0] a,
    input [15:0] b,
    output reg [31:0] p
    );

    reg [31:0] in2;
    wire [15:0] in;

    always@(posedge clk) begin
    p <= a*b*in2;
    in2 <= in2+1;
    end
    always@(in) begin

    in2 <= in1 ;

    end

    multi_test mu(
    .clk(clk),
    .i_am_output(in[15:0])
    );
    endmodule
    so above code will work fine right,,little changes from FvM's code
    is there any way to assign in to in2 immediately like blocking assignments or "assign" statement " (i need to synthesize it )

    thanks



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  8. #8
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    Re: Verilog: declaring variable as reg throws an error

    You aren't thinking about what your description (HDL) represents when it's supposed to be synthesized to hardware (HDL).

    Here is what you are describing in your code...
    Click image for larger version. 

Name:	Capture.PNG 
Views:	2 
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ID:	146541

    That shorted in1 and in2 can't be implemented in hardware either using Verilog or Systemverilog. You need to understand if you want to synthesize logic you cannot just use V/SV like a "programming" language you have to restrict your usage to only synthesizable constructs that can be realized in a piece of hardware.

    Shorting two outputs together does not work well in hardware as driver contention will burn out one or both drivers if they are at different logic levels. This is why there are tristate drivers, open-drain/collector drivers, etc to allow such shorted connections. In an FPGA there are no such drivers. So you can't write code like this (with multiple drivers) and expect it to compile.

    - - - Updated - - -

    I think it would help if you took a lot of simple HDL circuit descriptions for various basic code snippets like muxes, decoders, etc and synthesized each of them and look at the logic that is synthesized (schematic view) to understand how code is interpreted as logic. You've proven over many previous posts (including this one) that you need to work on understanding how synthesis interprets your HDL code and what logic it produces.

    If you choose to disregard this advice, then you will forever be force to continually return here and ask questions on fundamentally flawed code.


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  9. #9
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    Re: Verilog: declaring variable as reg throws an error

    yes,

    i got your point....multiple drivers.

    thanks ads-ee



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