dipin
Full Member level 4
Code:
module multiplier(
input clk,
input [15:0] a,
input [15:0] b,
output reg [31:0] p
);
reg [31:0] in;
always@(posedge clk) begin
p <= a*b*in;
in <= in+1;
end
multi_test mu(
.clk(clk),
.in(in[15:0])
);
endmodule
hi above is a demo for my problem,,,,"in" output of multi_test , i must used in two places like above (its demo).. but when i synthesize it , its throwing an error "in" must be a wire. but if i declare it as a wire i cant use it inside always block.
how to solve this?
did anybody came across this issue before ,any help is really appreciated
how to assign the value of wire to a reg?
UPDATE ..............................................
now i am doing like below
Code:
reg [31:0] in2;
always@(posedge clk) begin
in2 =in;
end
thanks and regards
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