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    For Xilinx If GWE release at the user clock edge, could the D flipflop misfunction

    Hi, nice guys,

    As you konw, the GWE of XILINX FPGA is synchronous to config clock. If the GWE released at the user clock edge, could the D flipflop misfunction?
    I find something which confused me. The D flipflop's init value is 0. The D flipflop is set to SRLOW. The D input is connected to logic 1, the SR is also connected to logic 1.
    I think the SR is high prioprity. So the D flipflop should be 0 at output. But we can get a clock cycle of logic 1 occasionally at the D output when start up.
    Could anybody give some comments?

    Thanks in advance!

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    Re: For Xilinx If GWE release at the user clock edge, could the D flipflop misfunctio

    Hi,

    There is a Xilinx Answer Record for GWE. It might help.
    https://www.xilinx.com/support/answers/44174.html
    .....yes, I do this for fun!



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