Signals in the verilog code not visible of Chipscope

Hello all,
I have written a code in Verilog and trying to simulate it using a booth multiplier. The simulation is working fine. I have many modules in my program. When i am trying to debug using chipscope, out of many signals, only 3 signals are visible on chipscope. Could anyone guide me on this? How can i see all my signals on chipscope?

If you are using ISE then use keep attribute on signals you want to connect in chipscope.
If you are using Vivado, then use mark_debug attribute on anything you want to have in chipscope.

Given you're trying to debug in Chipscope a design that "simulates" okay probably means you did not code your design properly and are having synthesis/simulation mismatches. As you refer to you code as a program...did you use a lot of for loops?

I've almost never seen a design that correctly stimulates using a simulation testbench that fails to work on hardware unless there was a tool bug or some missing corner case that the testbench never checked.

The times I've resorted to using chipscope have always been to determine a hardware/software integration problem or a system behaviour problem, but never to debug my HDL code.