Boost PFC stage should NOT provide an almost perfectly sinusoidal mains input current

Do you agree with the following…
The theoretical idea of a Boost PFC stage is to make mains input current sinusoidal and in phase with the mains input voltage.

..However, in practical terms, that is not the ultimate goal.

The ultimate goal is to make a Boost stage which passes the regulations on PFC (EN61000-3-2), without necessarily providing a perfect sinusoidal input current. In fact, what you really want is a Boost stage which passes the PFC regulations and yet has a fast-as-possible transient response, and also stays stable under all conditions.
…And in fact, if your boost PFC stage is producing an almost perfectly sinusoidal mains input current, then it will not be properly optimised in these practical terms.
Do you agree?

Hi,

any non-sinusoidal current means distortions - or in toher words "overtones".
Nowadays devices must meet regulations not to cause too much overtones.

So - not causing overtones - means that the current should be sinusoidal.

Klaus

if your boost PFC stage is producing an almost perfectly sinusoidal mains input current, then it will not be properly optimised in these practical terms.
Do you agree?

Click to expand...

Generally not, you can design a PFC controller that produces almost perfect sinusoidal current without affecting other performance parameters. But for a particular design, when using a specific PFC controller IC, a compromise may be appropriate.

you can design a PFC controller that produces almost perfect sinusoidal current without affecting other performance parameters.

Click to expand...

That seems contradictory to me.
The outer voltage loop speed has a direct impact in the harmonic generation. What "other performance parameters" besides crossover frequency (of the voltage loop) are you referring to ?

Yes, high voltage loop bandwidth versus low THD is a trade-off in standard PFC controller topology. To optimize both parameters, a PFC controller must utilize additional control principles, e.g. load current feed forward. That's why I said you can design a PFC controller with almost perfect sine current shape.

As an example, the UCC28070 is a controller with quantized feedforward to improve PF while maintaining high voltage bandwidth.

Most of the tradeoffs in performance you make are governed by the actual components available to you, not some fundamental theorems of physics. That's why it's senseless to try and discuss optimization outside of specific cases where the components are known.

And the allowable bill-of-materials budget is known.

If your PFC stage processes power at 1.00 PF then it is drawing the MINIMUM current from the AC supply (disregarding really flat topped mains for the discussion)

any variation from 1.00 PF means you are drawing reactive power now too, and hence more current and hence more losses.....

So for maximum efficiency => 1.00 PF

The biggest positive effect from a good boost stage is that it is slow...! yes slow = good, because if the Vrms suddenly goes up a booster can't help but draw more current for a cycle or so until it re-stabilises, and if the V mains goes down the input current goes down too for a few cycles - this is very good for the stability of the grid if you have a lot of electronic power processors ( power supplies etc) on the line - as the effect is towards stable.

If the input PFC stage was truly constant power (as some are trying to be) then too many on the line would tend to make the local grid unstable.

This is one of the true but little realised unintended benefits of the two stage power supply - guaranteed grid stability - due to the slow volt loop of the booster...

it should probably be mandated ...

Most of the tradeoffs in performance you make are governed by the actual components available to you, not some fundamental theorems of physics. That's why it's senseless to try and discuss optimization outside of specific cases where the components are known.

Click to expand...

Thanks, yes, in this case , i am speaking of a Boost PFC stage made with an LT1248 power factor corrector IC. -Just the simple configuration of it as in its datasheet

LT1248
https://www.analog.com/media/en/technical-documentation/data-sheets/1248fd.pdf

The LT1248 seems to be an exact copy of the UC3854, right down to the 7v5 ref ....

Thanks thats interesting, and i note in the UC3854 datasheet they call for a protection diode from the multout pin to ground, whereas the LT1248 datasheet makes no mention of this.

UC3854
https://www.ti.com/lit/ds/symlink/uc3854.pdf