Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence Encounter place and route - Pins not covered by metal layer

Status
Not open for further replies.

NikosTS

Advanced Member level 4
Joined
Jan 30, 2017
Messages
119
Helped
1
Reputation
2
Reaction score
2
Trophy points
18
Activity points
1,054
Hello everyone,
After placing and routing a design , i see that the pins are not covered by the metal layer that was used for the routing. This results in DRC errors when the design is imported in Cadence Virtuoso.
Is there any way ( option for example ) that can fix this problem? On my design there are around 160 pins so it will take quite some time to fix them manually.

Thank you in advance
 

Hello everyone,
After placing and routing a design , i see that the pins are not covered by the metal layer that was used for the routing. This results in DRC errors when the design is imported in Cadence Virtuoso.
Is there any way ( option for example ) that can fix this problem? On my design there are around 160 pins so it will take quite some time to fix them manually.

Thank you in advance

What pins? The top level pins or internals? Which layer did you use, what are you expecting to see?
 

The top level physical pins, for which i used the lowest layer ( metal 1 )
 

The top level physical pins, for which i used the lowest layer ( metal 1 )

They shouldn't be in M1 to begin with. But that is another problem. What are you expecting to see that you are not getting? I don't understand this "pin covered by metal layer" issue. Either the pin is there or it isn't.
 

The pin, that is on layer M1 with purpose "pin" is not fully covered by layer M1 with purpose "drawing" that is used for routing. That issues a DRC error " Pin not fully covered by metal X " .
By the way, why they shouldnt be on layer M1?
Thank you
 

For lower level blocks M1 is fine if that's the "natural" routing
layer for a particular signal. But putting M1/pin on a M6/drawing
path will not assign any connectivity.

For full chip routing you really ought to put the pins on the
topmost (pad-exposed) metal to ensure that connectivity
extends all the way out.
 

This digital block will be used on as a part of a mixed-signal system, so the pins will not be connected to any pads, but only to other internal pins of the system
 

The pin, that is on layer M1 with purpose "pin" is not fully covered by layer M1 with purpose "drawing" that is used for routing. That issues a DRC error " Pin not fully covered by metal X " .
By the way, why they shouldnt be on layer M1?
Thank you

This seems like a layer mapping/GDS import issue. There is no physical meaning behind layer purpose, it is not important.
 

The "pin" purpose is important for LVS though so i can't go past it.
The thing is that even on Encounter the pins ( layer M1 "pin" purpose ) are not fully covered by the routing metal .
 

The "pin" purpose is important for LVS though so i can't go past it.
The thing is that even on Encounter the pins ( layer M1 "pin" purpose ) are not fully covered by the routing metal .

LVS is a different problem, you were talking about DRC before. Design should be DRC clean no matter the layer purpose. As for LVS I'd still think it is an issue with layer mapping/GDS import.
 

Maybe an issue with the abstract generation? Did you check your .lef file?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top