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    Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hello EDAboard

    I have been struggling with parasitic extraction using Calibre of my TSMC018 4-stage gate-driver.

    Currently I have been unable to find a PDK/tech specific guide to using Calibre for PEX, I have however tried to figure it out myself.

    The only issue is now, that the resulting PEX I open in Calibre view does not set nets to my extracted MOSFETs (the gate-driving MOSFETs, one for each number of fingers present).

    I can clearly see all the parasitic resistors and capacitors have labels on their pins, but the corresponding gate-drive MOSFETs have not and remain floating on all pins.


    I was wondering if you guys knew of this issue OR, do you know if TSMC018 usually containts a guide to using Calibre for PEX?

    I have been told that various PDKs use various techniques, and some even require you to draw extra layers and stuff.

    Best regards Jacob

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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    A couple of questions:

    * Is the calview.cellmap file properly defined and
    * do you get a netlist of out the RCX/PEX that looks reasonable? Missing connections there too?

    The latter should be OK in case LVS passes (which it does, I presume, since you are able to start the PEX)?



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hello jjx

    1. The calview.cellmap should be quite fine.
    2a. I both pass the standalone LVS and I pass the LVS automatically run when doing a PEX.
    2b. Regarding the PEX netlist, I am not 100% sure I am looking at the right one. Current I look at the .pex.netlist file. The list starts out with some metainformation, a long list of device templates and then mgc_rve_cell_start followed by some component definitions I suppose.

    By looking at this I see the following statement:

    mr_pi "nch_5" "MM0" '( "MM0_d" "MM0_g" "MM0_s" "MM0_b")

    Where nch_5 is the single NMOS I am trying to extract from. I did NOT call it MM0 but only M0. So maybe the issue is that PEX adds an additional M?



    •   Alt9th May 2018, 13:20

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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Did you try to run simulation with your post-layout netlist?
    Then you should be able to see right away, if your MOSFET instance pins are floating or connected to the R networks of G/D/S/B nets.

    Extraction tools may add extra "M" or "X" to the instance names - that is configurable using extraction tool commands.

    PDKs for extraction tools may be capricious - the unspoken assumption here is that you can contact your extraction tool vendor and ask for support.
    If you are a big and important company, they will respond immediately. If not - good luck to you.

    The typical output from parasitic extraction is DSPF file format - it should contain the following items / statements:

    .SUBCKT - defining the top level subcircuit

    *|NET ... - for each of the extracted nets

    C... - parasitic capacitors (line should start with "c" or "C")

    R... - parasitic resistors (line should start with "r" or "R")

    * Instance Section - that should list all the extracted devices, with their layout-dependent instance parameters and values

    ------------------



    •   Alt9th May 2018, 18:18

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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hello timow thank you for your reply and suggestions.

    I have tried simulating my extracted view, did not work unfortunately. And whenever I try to save the calibre view of the extracted layout, I get xxx errors saying floating nodes.
    By inspection in the Calibre view I can clearly see the MOSFET's pins being floating.

    Ah, interesting with the M/X. So it will not cause any issues? How does it know that when the schematic symbol is called M0 it should be using MM0 instead?

    Yeah, we are already dealing with TSMC here. They only like you if you pay the big bucks, unfortunately I am just at a reasonably small university, so the support is non-existing. Furthermore the documentation is crap.

    Regarding the DSPF file format I am not able to find it, unfortunately to check up on the netlist. Should it be ending on .DSPF?

    The only thing actually describing my extracted circuit is this:

    mgc_rve_cell_start "project_name" "VDD" "IN" "VSS"
    mr_pi "nch_5" "MM0" '( "MM0_d" "MM0_g" "MM0_s" "MM0_b") '( ("l" 6e-07) ("w" 2e-06) ("ad" 9.6e-13) ("as" 1.08e-12) ("pd" 4.96e-06) ("ps" 5.08e-06) ("nrd" 0.24) ("nrs" 0.27) ("sa" 1e-06) ("sb" 4.8e-07) ("sca" 2.09172) ("scb" 0.000655181) ("scc" 8.35419e-06) ("lpe" 2) ) '(0.5 1)

    mr_ni "VDD" 5.35622 0 0 '( "MM0_d" )
    mr_pp 'r "rVDD_0" '("VDD_11" "VDD_12") 2.75
    mr_pp 'r "rVDD_1" '("VDD_9" "VDD_11") 0.761348
    mr_pp 'r "rVDD_2" '("VDD_7" "VDD_9") 0.0435808
    mr_pp 'r "rVDD_3" '("VDD_7" "VDD_8") 0.271304
    mr_pp 'r "rVDD_4" '("VDD_3" "VDD_8") 0.0435808
    mr_pp 'r "rVDD_5" '("VDD_3" "VDD") 0.503609
    mr_pp 'r "rVDD_6" '("VDD_2" "VDD_12") 0.1092
    mr_pp 'r "rVDD_7" '("VDD_2" "MM0_d") 0.8736


    mr_ni "IN" 22.8784 0 0 '( "MM0_g" )
    mr_pp 'r "rIN_0" '("IN_10" "MM0_g") 18.2217
    mr_pp 'r "rIN_1" '("IN_9" "IN_10") 3.9
    mr_pp 'r "rIN_2" '("IN_4" "IN_9") 0.170024
    mr_pp 'r "rIN_3" '("IN_4" "IN") 0.586696


    mr_ni "VSS" 8.6533 0 0 '( "MM0_b" "MM0_s" )
    mr_pp 'r "rVSS_0" '("VSS_13" "VSS_20") 0.0940792
    mr_pp 'r "rVSS_1" '("VSS_13" "VSS_15") 0.0346154
    mr_pp 'r "rVSS_2" '("VSS" "VSS_20") 0.447652
    mr_pp 'r "rVSS_3" '("VSS_3" "MM0_s") 0.9828
    mr_pp 'r "rVSS_4" '("VSS_3" "VSS_24") 0.9828
    mr_pp 'r "rVSS_5" '("VSS_3" "VSS_15") 2.75
    mr_pp 'r "rVSS_6" '("MM0_b" "VSS_24") 0.86135
    mr_pp 'r "rVSS_7" '("MM0_b" "VSS_15") 2.5

    mgc_rve_cell_end
    Does this look familiar?



    •   Alt9th May 2018, 20:30

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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    This does not look like DSPF at all.
    This looks like a mixture of device templates with point-to-point (pp?) resistance simulations (from PERC?).

    There should be a command/switch in Calibre PEX instructing the tool to generate DSPF file format.
    Its extension can be whatever you specify, .dspf or .pex.netlist, etc.

    How the flow treats device names is its internal matter - you will be interacting with the netlist through its ports - which names stay constant (usually the same names in both schematic and layout).
    (if you want to probe or measure elements - I think the flow allows you to specify the original schematic names).

    What you describe, regarding foundry support, documentation, etc. - sounds pretty much like industry standard, state of the art in EDA / IC design.

    calview.cellmap file defines mapping of device pin names between Calibre name space and Virtuoso name space (for example, PLUS to POS for diodes and capacitors, etc.).

    I think your extraction flow / setup or PDK is missing some important elements, some files or settings.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Very interesting.

    I am running the Calibre Interactive - PEX and not PERC, but I suppose there could be something wrong with our PDK setup.

    The pp definitions of resistors and stuff I can clearly see in the calibre view of the extracted schematic, so it must be partly correct I suppoe.

    Regarding the DSPF file format, I can set the output netlist format to CALIBREVIEW, DSPF, ELDO, HSPICE, SPECTRE og SPEF. I suppose this might be the configuration ability you were refering to.

    An old AMS process I used required the output to be Calibreview, so I just went with that.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Calibre PEX (xRC), or any other extraction tool (StarRC, QRC, etc.) does not produce the file format you showed here - U suggest you to specify DSPF as output format and inspect it.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    CalibreView is specific to Cadence tools; if you are not running a Cadence flow with Calibre just for DRC/PEX, you are better off with one of the other spice-based formats. Also, every so often Cadence changes their API and it can take Mentor a release or two to catch up. I think the currently supported versions (from the Calibre Interactive standpoint) are documented in the "Interfacing with Layout and Schematic Viewers" appendix in the calbr_inter_user.pdf.

    For DSPF, ELDO, HSPICE, and SPEF, the formats are open standards so you shouldn't have any versioning problems, and chances are they'll be accepted by all downstream tools.

    If you are still having trouble with floating nets, take a look in Calibre Interactive - PEX, PEX Options > Netlist > Format for the "Extract Floating Nets" options.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Quote Originally Posted by timof View Post
    Calibre PEX (xRC), or any other extraction tool (StarRC, QRC, etc.) does not produce the file format you showed here - U suggest you to specify DSPF as output format and inspect it.
    Hi timof. Thank you very much for your reply.

    Interesting regarding the file output. I have recently tried producing a DSPF output and I believe it looks pretty much like it should, even though it is very lengthy. However it does not seem to make any difference, when I try to simulate my DSPF output of the gate-driver using the config file.

    - - - Updated - - -

    Quote Originally Posted by slizak View Post
    CalibreView is specific to Cadence tools; if you are not running a Cadence flow with Calibre just for DRC/PEX, you are better off with one of the other spice-based formats. Also, every so often Cadence changes their API and it can take Mentor a release or two to catch up. I think the currently supported versions (from the Calibre Interactive standpoint) are documented in the "Interfacing with Layout and Schematic Viewers" appendix in the calbr_inter_user.pdf.

    For DSPF, ELDO, HSPICE, and SPEF, the formats are open standards so you shouldn't have any versioning problems, and chances are they'll be accepted by all downstream tools.

    If you are still having trouble with floating nets, take a look in Calibre Interactive - PEX, PEX Options > Netlist > Format for the "Extract Floating Nets" options.
    Hello slizak. Thank you for replying to my thread.

    Regarding the calibr_inter_user.pdf I fail to find it on my available workstation, so I will ask around my deparment for Calibre documentation. Lovely knowing DSPF and the like will be very compatible, it easily limits your design capabilities having to deal with software versioning.

    Thanks for the floating nets suggestion, even though it seems to make no difference atm whatsoever.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hi JE-

    The Calibre documentation is typically in the installation directory. (There were some releases around 2010 or 2012 that did not include it because the download had become so large.) Assuming the installation set the correct variables, you should be able to get it from the Calibre Interactive Help menu or look in $CALIBRE_HOME/docs/ .



    •   Alt14th May 2018, 21:11

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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    In DSPF file, at least you can explore connectivity, to see where / if devices are connected to nets.



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hello everyone. Thank you very much for your assistance, I have solved the issue. It currently works using Calibreview as output file, using either "masklayout" or "schematic" as Calibre view type works splendidly.

    Fixing the following errors solved the problems I have been having:
    - The wrong file calview.cellmap was used. Instead of the PDK specific cellmap, it used a local empty cellmap.
    - In order to use _mac models from TSMC, you have to #DEFINE MACRO in SVRF commands

    Again I would like to express my deepest gratitude towards the guys of you who have helped me with.


    Best regards
    Jacob



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    Re: Calibre Parasitic Extraction of TSMC018 Gate-Driver

    Hey Jacob -

    thanks for your follow up, and for explaining what was the problem.

    Yes, calview.cellmap (or a similar file, in newer PDKs) is often at fault.
    This file maps terminal names (between Calibre and Virtuoso name spaces), and when mapping is wrong - your devices become disconnected form the nets.

    It's also good to learn about #DEFINE MACRO command in Calibre SVRF.



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