Low Dropout Regulator Testbenches and Simulation

Hello,

I am looking for test benches and simulation considerations for Low Dropout Regulators in CMOS in Cadence or Spice.

I am particularly looking for how to change the output load and see the effect on the voltage output - how would I modify the output load in say Cadence ? Also looking for other test benches and simulation considerations and suggestions to characterize the LDO.

Any suggestions on books, papers, theses or other resources for simulation of LDOs ?

Thanks.

Le t me give you a hint..
Think that being as a practical case.When you measure transient response of a regulator, you change the load abruptly and observe the response.
Do it similarly in Cadence ADE.Do a transient simulation with a fixed load and then change the load ( connect another load through a switch that is controlled a PW Linear Voltage source ) and observe the variation/fluctuation.

Make the load a charging capacitor, if you wish to make Ampere draw decrease gradually.

Make the load an inductor, if you wish to make Ampere draw increase gradually.

In most papers I see the load is a current source, so do I put a resistor, capacitor or inductor ?

I guess as BradtheRad said a C or L. Correct ?

Puppet123 said:

In most papers I see the load is a current source, so do I put a resistor, capacitor or inductor ?

I guess as BradtheRad said a C or L. Correct ?

Click to expand...

Current Source is also fine.You increase the current in time by certain amount the observe what'll happen..

Current source and resistor loads do have different
behaviors in some cases - especially at light load in
a PMOS regulator, big difference in Zout and the
stability is possible. You might try both at a few
current points.

You also ought to determine the min and max C
and any ESR limits, for the output filter. You can
find "zero cap" LDOs and you can find LDOs that
want output caps, but are picky about the ESR of
those caps.

It's a multi-variable application space and your
"customers" (if any) would like to have good design
guidance.

Take some care in specifying the load step edge
rates. Too leisurely and you test nothing; too fast
and you'll never be able to hold down the overshoot
/ undershoot and pull in the settling time well enough.
Find something either realistic, of commonly-done
(read LDO datasheets for load-step waveforms and
descriptions of the test conditions).