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  1. #1
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    Creating an FPGA accelerator in 15 minutes

    hI,

    i am usimg 16 processor parallella board .
    my os is opensuse.

    when i am trying to implemet this : https://www.parallella.org/2016/01/2...in-15-minutes/
    i am getting
    CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'system' instantiated as 'system_i' [/home/dipin/development/fpga_arm_proj/oh/src/accelerator/fpga/system.srcs/sources_1/bd/system/hdl/system_wrapper.v:16]
    basically system_wraper is an ip file , and in directory there is no "system_i.

    next i am getting an error
    ERROR:Black Box Instances: Cell 'system_i' of type 'system' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
    ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.
    i google the error few suggestions are like its because of vivado versions and i didn't find how to fix it..
    next errors are
    ERROR: [Common 17-69] Command failed: Run 'impl_1' failed. Unable to open

    [ERROR] : Can't read BIT file - ./system.runs/impl_1/system_wrapper.bit cp: cannot stat 'system_wrapper.bit.bin': No such file or directory
    did anybody know how to fix it.. any help is really appreciated

    thanks and regards

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  2. #2
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    Re: Creating an FPGA accelerator in 15 minutes

    I have not looked at the project details.

    As you say there is an IP and it is being treated as a black-box, re-check if the "Generate Output Products" for this IP have successfully completed or not!
    .....yes, I do this for fun!


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  3. #3
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    Re: Creating an FPGA accelerator in 15 minutes

    It is a block design. You have to open it and then run generate on it, that will produce the bd design files.


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