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    Multilayer inductor parameter measurement with VNA

    I made some multilayer inductors in standard CMOS process with variable inductance. Design principle is similar to this example :
    Click image for larger version. 

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    Park, P.; et al. 2004. Variable Inductance Multilayer Inductor with MOSFET Switch Control, IEEE Electron Device Letters, vol. 25, 144–146.

    In order to compensate parasitic elements I shorted two pads in the IC design. So my Idea for testing basically was to measure S11 (I have PocketVNA) of my inductor, convert to R and X, measure S11 of my short circuit in IC, convert to R and X, subtract one from another, because parasitic elements connected in series with inductors.

    My one of test boards and measurement rig:
    Click image for larger version. 

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    Click image for larger version. 

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    However I got results which are back to front e.g.:
    each time I open one of control NMOS I get increased inductor resistance and bigger total inductance. In theory it should be opposite, NMOS channel is parallel connected to the part of inductor, at worst inductor resistance should stay similar than before, same with inductance. I measured inductor resistances with dumb multimeter and indeed i got smaller resistances each time I opened a NMOS transistors.

    Either my VNA have not enough resolution and parasitic elements are too big compared with actual inductor or my measurement methodology is incorrect.

    All advices how to properly measure inductor parameters (R, L, Q, fsr) are welcome.

    PS. I tried to calibrate VNA through short circuited pads, but results were way off. I don't have access to better VNA.

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    Re: Multilayer inductor parameter measurement with VNA

    In such measurements "In-Line Calibration" is important.So that, calibration reference should be in-line with inductor reference.
    the second thing, I guess the internal connections of the MOS transistors present more inductor/resistor so MOS transistors don't provide a ideal short circuit internally.
    Since you don't know these internal connections, extraction is impossible.It also depends on the frequency..
    So many thing can be happen but we have a very little information.



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    Re: Multilayer inductor parameter measurement with VNA

    How about my measurument methodology? Is it legit at least in theory?
    1)Measure shorted IC pads (parasitics).
    2)Measure inductor (DUT+parasitics).
    3)Subtract one from another to get R and X of DUT.



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    Re: Multilayer inductor parameter measurement with VNA

    First,we need to Understand what types of amplifier measurements are made
    with RF VNAs.
    • S-parameter / Stability factor (K-factor)
    • Measurements with power leveling
    • Gain compression (P1dB compression point)
    • Pulsed-RF measurements
    • Intermodulation distortion (IMD)



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    Re: Multilayer inductor parameter measurement with VNA

    The above quote from a Keysight paper https://www.keysight.com/upload/cmc_...th_VNA_pdf.pdf
    isn't related to the thread discussion at all.

    - - - Updated - - -

    How about my measurement methodology? Is it legit at least in theory?
    If the reference plane is shifted to the IC pads, you can measure a lumped impedance between the pads. Relevant parasitic elements like bond wire inductance and parallel capacitance can't be however compensated by a short measurement.



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  6. #6
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    Re: Multilayer inductor parameter measurement with VNA

    What is the value of your on-chip inductor that you try to de-embed?



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