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PEX C capacitance - Huge delay in postlayout simulation

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AlQadasi

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Hi all,

After doing some layout, I found out that the delay increase is 50%. I am getting a 6ps input-to-output delay in prelayout simulation, but getting more than 9ps delay in the postlayout simulation. The C-parasitic capacitance (between ground node and substrate) is so huge (in the 0.5fF range for some nodes) even though I am doing the layout for a simple inverter.


In addition, I am getting some warnings in the PEX about the layers not being mapped. Has anyone experienced this before? Is that an issue in the PDK I am using?


Thanks
 

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Last edited:

This all unsurprising for a minimum inverter and any kind
of line length. You could probably find fF/um or fF/um2
numbers in the PDK docs if you want to sanity-check the
extracted result.

Check that you have not simply used improper layer/purpose
for your polygons/paths - like, use Met1/drawing, not
Met1/net or whatever. Again you could go to the PDK docs
or the layertable to see what datatype means, in the kit.

The nplug/pplug stuff, I'd guess means a wrong choice about
how to do body ties / taps - or that the actual connection
needs something more (like, maybe "pplug" is a "recognition
layer" that should mark a pplus contact to sub!).
 

50% delay increase is not surprising.

Error messages in parasitic extraction may mean something is not configured properly, so the results may be bogus: "garbage in - garbage out".
 

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