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Delay in pipeline ADC switch

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akbarza

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Hi
In below figure, why must Q2' fall before Q2? And how can we make Q2' from Q2? Is important the delay value between Q2, Q2'? if it is ok, what the delay value must be?
If you know a reference about this, please introduce it to me, thanks.

2.PNG
 

I guess the picture is not fully complete and it would be a bit more visible in a grander scheme.

However, books/papers dealing with offset-cancellation switched-capacitors gives some clues. The issue is that you want to remove the opamp slightly before any other changes such that the voltages are kept. But, as mentioned, probably more visible when looking at how it is connected to the other stages.

You would most likely generate Q2 as function of Q2' instead and then some inverters and an OR-gate or similar logic configuration can be used.
 

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