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    Tracing internal signals in Modelsim

    Hello

    I am running a simulation of a digital design for Virtex 5 FPGA in Modelsim simulator (PE student edition 10.4a).

    Currently I am able to trace all the top entity signals in wave window, however I want to trace the internal signals of the design as well,
    which are not visible in the object window itself.

    Although I can easily trace all the internal signals in ISIM.

    So my query is, is this a limitation to Modelsim as a simulator or the student edition has these limited features.

    Please provide your inputs.

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    Re: Tracing internal signals in Modelsim

    You need to select the individual design modules in the object hierarchy to see its internal signals.

    Selection in the sim window instance hierarchy:

    Click image for larger version. 

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    Re: Tracing internal signals in Modelsim

    An easy way to add everything is from the console window:

    add wave -recursive *


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    Re: Tracing internal signals in Modelsim

    Thanks to both of you..

    Both of these solutions proved helpful for behavioral simulation.

    But if I am doing post layout simulation the names of all the internal signals changes.

    So my query is there any way to trace these names back to the original names used in the source code (VHDL code.) so that relevant signals can be traced in the wave window.



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    Re: Tracing internal signals in Modelsim

    If the design isn't too big, I normally do
    add log -r /*
    before starting simulation.
    In that way, I can at any time add any signal to the wave window and see everything from the start of simulation.
    It is also easy to arrange the wave signals for the current debugging needs.
    If I have to make a change in the code and restart simulation, I first save the waveform window setup to a file, so I easily can get the same signals in the next run.

    When adding everything to the wave window from the beginning, I find it much more difficult to do debugging, because a lot of non-interesting signals take space.



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    Re: Tracing internal signals in Modelsim

    Quote Originally Posted by std_match View Post
    If the design isn't too big, I normally do
    add log -r /*
    before starting simulation.
    In that way, I can at any time add any signal to the wave window and see everything from the start of simulation.
    It is also easy to arrange the wave signals for the current debugging needs.
    If I have to make a change in the code and restart simulation, I first save the waveform window setup to a file, so I easily can get the same signals in the next run.

    When adding everything to the wave window from the beginning, I find it much more difficult to do debugging, because a lot of non-interesting signals take space.
    In which file format do you save the waveform window set up, which can be recalled in the simulation run.

    And second thing, as already asked in post #4, how do you relate internal signal names in post layout simulation to the original names in source code



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    Re: Tracing internal signals in Modelsim

    Quote Originally Posted by mjuneja View Post
    In which file format do you save the waveform window set up, which can be recalled in the simulation run.

    And second thing, as already asked in post #4, how do you relate internal signal names in post layout simulation to the original names in source code
    In the waveform window, you click File -> Save Format
    The default file name is "wave.do" and it is a text file with a lot of "add wave" commands.

    The easiest way to get the waveform window back in the next simulation is to enter "do wave.do" in the command line.
    Don't forget to "Save Format" again if you add more signals that you want in following simulation runs.

    I have no solution to the post synthesis/post layout problem.
    Why simulate post layout for an FPGA? It is only relevant if there is a bug in the toolchain.
    The only thing I do post-synthesis is to insert chipscope and connect the interesting signals. Sometimes, the signal you want doesn't exist, or you can't find it.



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    Re: Tracing internal signals in Modelsim

    Dear, for post synthesis and post layout simulations , the internal signals of the design are named according to the technology implemented so you need to check RTL and Technology implantation to check how signal names are changed w.r.t to your original design signal and registers declared in your HDL file.



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    Re: Tracing internal signals in Modelsim

    For post-synthesis, the names might not exist any more. If you have specific nets you want to keep, you would need to mark them with KEEP, IIRC.

    For modelsim can also be useful to use -voptargs="+acc"
    however, I doubt this is useful for post-synthesis simulation.



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    Re: Tracing internal signals in Modelsim

    Quote Originally Posted by vGoodtimes View Post
    For post-synthesis, the names might not exist any more. If you have specific nets you want to keep, you would need to mark them with KEEP, IIRC.

    For modelsim can also be useful to use -voptargs="+acc"
    however, I doubt this is useful for post-synthesis simulation.
    "KEEP IIRC" property belongs to which process, I am using ISE design suite from Xilinx.



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    Re: Tracing internal signals in Modelsim

    IIRC = If I recall correctly
    KEEP = an attrbute you can directly apply in your HDL to tell the synthesis to keep your signal intact, including the name.

    eg, in VHDL, you write the following:

    Code VHDL - [expand]
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    signal sig1 : std_logic;
     
    attribute KEEP : string;
    attribute KEEP of sig1 : signal is "TRUE";



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