Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
There is a setup time requirement from the release of an async reset to the rising edge of clk in order to prevent metastability. This could be a glitch or it could be mean that the reset is released one cycle later.
This requirement only applies when you are trying to change state when you release reset. If you async reset to 0 and have a 0 sitting on your D input then there is no requirement.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
