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  1. #1
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    Define 2 dimensional localparm in Verilog

    Hello all,

    I'm trying to define a set of coefficients for some DSP inside a FPGA but I'm running into a problem with defining the coefficients. I want a 1000 element array with each element being 18 bits. I'm running the below code:
    Code Verilog - [expand]
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    localparam num_taps = 1000;
    localparam coeff_scale = 16;
    localparam signed[17:0] coeff[0:999] = '{0, 3, 5, 8, 9, 10, 10, 9, ...};

    When running this I get an error this error:
    Code:
    ERROR:HDLCompiler:806 - "filter_coeff_15.h" Line 3: Syntax error near "'".
    So it doesn't like the single quote for some reason but I don't understand why. My understanding is that this is how you would define an array like this. I use this code with Modelsim and it works perfectly. Why does ISE not like this?

    I've tried removing the single quote and it seems to work but I think it's doing something weird and thinking this is a single 18000 element.

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  2. #2
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    Re: Define 2 dimensional localparm in Verilog

    Is this valid Verilog? It works in SystemVerilog. I don't think SV was ever added to ISE. you might need to just make it a reg and initialize it in an initial block. That also might allow for initialization using readmem.



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  3. #3
    Member level 3
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    Re: Define 2 dimensional localparm in Verilog

    You're correct, it appears to be System Verilog syntax. I tried what you suggested by initializing it in a initial block and that worked. And you're right that readmem can do the same thing. Thank you!



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