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setting attributes to VHDL entity ports

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shaiko

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Hello,

In VHDL, Is it possible to set attributes to VHDL ports?
I know the syntax for setting an attribute to a signal - but what about a port?
 

yes. In the same way you assign attribute to signal:

attribute keep of some_port : signal is "true";
 
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    shaiko

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I've also seen suggestions to use:

attribute keep of some_port : port is "true";

Not sure if the tools accept both.
 

attribute keep of some_port : port is "true";
This is exactly what I tried before posting - and it didn't work with Vivado...
 

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