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  1. #1
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    setting attributes to VHDL entity ports

    Hello,

    In VHDL, Is it possible to set attributes to VHDL ports?
    I know the syntax for setting an attribute to a signal - but what about a port?

    •   Alt27th April 2018, 15:26

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  2. #2
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    Re: setting attributes to VHDL entity ports

    yes. In the same way you assign attribute to signal:

    attribute keep of some_port : signal is "true";


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    •   Alt27th April 2018, 18:19

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    Re: setting attributes to VHDL entity ports

    I've also seen suggestions to use:

    attribute keep of some_port : port is "true";

    Not sure if the tools accept both.



    •   Alt29th April 2018, 06:04

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  4. #4
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    Re: setting attributes to VHDL entity ports

    attribute keep of some_port : port is "true";
    This is exactly what I tried before posting - and it didn't work with Vivado...



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