implement DFF by loop

wittman · Apr 27, 2018

Hi, to implement N DFF with one single clock, we can use for loop. For example

Code:

parameter N;
integer i;
reg [N-1 : 0] dff_cell, dff_cell_next;
always @(posedge clk)
  for(i=0;i<100;i=i+1)
     dff_cell[i] <= dff_cell_next[i];

But, how to implement N DFF with N different clock by for loop (or other method)?
Because there is error message if i write such code

Code:

parameter N;
for (i=0;i<=100;i=i=1)
  always @(posedge clk[i])
    ........

The parameter "N" will be config by other user, so I can make sure what it will be.

ads-ee · Apr 27, 2018

It has to be in a generate statement.

ThisIsNotSam · Apr 27, 2018

I struggle to find a reason one would want to do this but... yes, use the generate statement.

FvM · Apr 27, 2018

Consider that most FPGA have limited number of clock networks, if the clocks are actually different, the 100 DFF design implementation may fail.