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[SOLVED] transient overshoot of pulse generator

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chandlerbing65nm

chandlerbing65nm

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Hi edaboards!

I just want to ask how to eliminate the overshoot of my pulse generated by using a comparing vref and ramp. Thanks
 

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Seriously? All you show is a picture and we are supposed to figure out what's wrong with your circuit??
 

barry said:
Seriously? All you show is a picture and we are supposed to figure out what's wrong with your circuit??
Click to expand...

What circuit should I show. I just use a pmos OP without compensation for the comparator and inverter with minimum aspect ratio in 65nm.
 

Hi,

I don't know if slowing the rise time slightly would remove that overshoot. You know I don't know much at all about CMOS stuff, to say the least. Maybe adding resistance and/or capacitance to the switch(es) gates to slow and therefore smooth rising edge, if that's how you're making it.
 

What circuit should I show. I just use a pmos OP without compensation for the comparator and inverter with minimum aspect ratio in 65nm.
Click to expand...
Looks like you know where to start. Next point is to analyze the actual circuit behavior and find out how the overshoot is brought up.

By the way, why do you expect that the circuit has a perfect square wave output? That happens rather seldom in real circuits.
 

First off, you don't know whether this is real or a simulation
artifact.

Second, you probably don't have all of the parasitic loading
that would swallow up glitch energy and make the edges
more leisurely.

Third, this looks like "so what?" to me. Can you name one
negative consequence of such a little overshoot?
 

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