# Nonconstant index in Verilog

1. ## Nonconstant index in Verilog

Hi
I want to check if "N" bits bus are all logic 1 and assign to the "pass" signal. The
bus width is variable and is defined by parameter N. But I get the "nonconstant index"
error message. How can I fix this issue?
Any help would be greatly appreciated!

Code:
```parameter N;//2~64
integer i;
reg [(N*N)-1 : 0] status;
reg [N-1:0] pass;
//pass is for status[N-1:0], pass is for status[(2*N)-1 : N] ... ,etc

always @(status)
for(i=0;i<=N-1;i=i+1)
pass[i] =  & status[N-1+(i*N) : (i*N)];``` •

2. ## Re: Nonconstant index in Verilog

If I interpreted what you are trying to do correctly...
Code:
`   pass[i] =  & status[(i*N) +: N];`
should do what you want.

Both the upper and lower bounds of a slice can't both be calculated

1 members found this post helpful. •

3. ## Re: Nonconstant index in Verilog

This is an artificial Verilog-ism. VHDL is totally fine with this -- other than lacking +:.

For Verilog, you can do:
Code:
```pass[i] =  &((status >> (i*N)) & ((1<<(N+1))-1));
// or
pass[i] =  &((status >> (i*N)) & (N){1'b1});```
although it feels like a hack.

I'd like to know if there are better solutions. I think the last time I tried this was 1 year ago, maybe Verilog allows +: with variable index now.

--edit: not sure on the precedence of >> vs *. either way it's probably not clear to many readers.

--edit2: actually, it looks like +: should work. I have no idea why it didn't the last time I tried it. maybe I made some other mistake. It looks like the LRM has an example for this case. If +: works, use it, it is a better construct anyways. •

4. ## Re: Nonconstant index in Verilog

Indexed part select syntax +: and -: is supported at least since Verilog 2001. --[[ ]]--