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[SOLVED] hanging source affects the system output

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chandlerbing65nm

chandlerbing65nm

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Hi all!

In my simulation of ramp generator, there is a bug (i think). When I put a vpulse source that is not connected to any nodes the ramp output is present, but when I delete the hanging source the output doesn't appear. The frequency of my ramp can be change differently by choosing charging capacitor value (I tried it). So it is not the vpulse source that cause the frequency of the ramp.

Any expert can help about this? I am using TSMC 65nm technology in synopsis cdesigner software.
 

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The problem may be one of having multiple valid initial
solutions, and changing the netlist (and the eventual
solution matrix) can change the one that "wins" for no
good reason, just "what happens" in DC solving attempt.

Consider yourself lucky if a simulation shows you this
kind of thing early on, and not (say) the night before
your tapeout review, or at FOK wafer probe.

You should be able to find the true reason for failure
to start oscillating, normal circuit debug. Don't blame
an element that should have no influence just because
it's what you touched last. The first thing you see is
not necessarily the only (or even, the) real cause.
 

My circuit is already working and I removed the hanging vpulse. But for my system to operate, my vdd should be vdd=0 at t0=0, meaning it should start at zero volt first then after some time, t1=t with vdd=vdd. I don't know if it is okay having a vdd that starts with 0V and not 1.2V at t=0.
 

You are seeing the supply ramp "push" an initialization
that a DC (or long timescale ramp) might not. Again this
is telling you to pay attention to startup -design-. Not
luck.

Imposing a range of supply risetimes as a requirement
on the user would not make you or your "product" any
friends. Don't be needy.
 

I just forgot to put initial condition in the charging capacitor. done.
 

Is this just another cheat? In real life, what range of initial
charges would be put on the cap, by whom and why?

I've seen digital ASICs bomb at probe because a designer
"passed" verification by applying resets (initial condition)
to the core when no real means to do so was part of the
netlist. This seems similar.

Also have seen things like POR circuits which work when
everything "ramps from zero" but won't work on a second
power cycle if a whole lot of bleed-down time was not
given.

Making it "work" and making it -work- are not always the
same. Although if it never gets past paper and phosphors,
maybe the sleight-of-hand will go unnoticed. If this was
going to be a real product I'd encourage you to develop
better habits, and perspective.
 

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