Mismatch simulation Schematic vs. Layout

Hello all Analog Design Experts:

Consider a simple scenario of mismatch between two transistors in a simple current mirror. Monte-Carlo simulation for mismatch-only in schematic points to some mismatch in currents (say few %).

We know the matching is affected by both schematic parameters (e.g. transistor sizes) as well as layout parameters (e.g. how close transistors are placed).

My question is when we do schematic simulation with Monte-Carlo for mismatch-only, how is the distance between transistors considered in the simulation? Does it assume transistors are placed as far as possible? Or does it assume they are placed properly close together?

Above question was specifically about transistor placement proximity, but in general, does the schematic simulation assume the worst layout (so once laid out, the results will be better)? Or does it assume the best layout (so once laid out, the results will be worse)?

Can someone please shed some light here? Thank you.

Regards,

DefconNowhere

Distance is not considered, unless you see some instance
property for distance and to-what. You have to know the
basis for the foundry's mismatch statistics extraction (which
often will be a minimum-spaced matched pair, taken over
a bunch of die sites, maybe wafers' worth). Given this (and
this is only from my experience with laying out many TCVs)
you have to assume that MM is for close devices and any
chip-scale effects are for you to analyze by other means.
Even temperature-aware simulators tend to look only at
intra-device self heating and not compile a whole die thermal
map, so don't expect temperature gradients to be shown.

It's nigh impossible to bound the worst case of bad layout
practice so don't expect modeling of it. If you care about
something, then lay it out right and hope for the best.

"lay it out right and hope for the best"

Click to expand...

There are EDA tools that do this verification automatically, so you do not have to hope, instead you verify and sleep well.

"My question is when we do schematic simulation with Monte-Carlo for mismatch-only, how is the distance between transistors considered in the simulation?"

Click to expand...

Schematic simulation does not know anything about layout, and hence knows nothing about layout-dependent effects affecting devices and nothing about layout parasitics - both of these can destroy your matching.

Thanks for your reply.

"There are EDA tools that do this verification automatically, so you do not have to hope, instead you verify and sleep well."

Click to expand...

Can you name some tools?

"Schematic simulation does not know anything about layout, and hence knows nothing about layout-dependent effects affecting devices and nothing about layout parasitics - both of these can destroy your matching."

Click to expand...

Schematic simulation should have an assumption of layout effects, otherwise schematic MM simulation would not show any variation but it does. So it assumes something and my question was does it assume best (close placement) or worst (far away placement). As it turns out, the schematic MM simulation assumes close placement and any layout simulation produces worse results than schematic unless it is really good.

Actually layout based simulation (in my experience) has
no additional clue regarding proximity - only the addition
of parasitic elements (C, RC, RCL depending on the
platform).

Everything depends to PDK and used models. Mosfets in more advanced CMOS nodes has proximity parameters (i.e. sa, sb and sc) affecting threshold voltage.

Monte-Carlo simulation is done with schematic net-list so the simulator does not know nothing about the layout.
It checks statistically "deviation from normal value" or shortly "what-if" scenarios.That's it..
It takes algorithmic values for each "process parameters" in the statistically measured limits of each process parameter ( not circuit model parameter ) and applies to model(s) then find the answer "what if" ..

These parameters account for "proximity" within the same device - not for statistical variation between different device instances.