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  1. #1
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    shift register , i have troubles when creating components please help!

    mux code
    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
     
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    entity mux is
    Port ( A0,A1,A2,A3,S0,S1 : in STD_LOGIC;
    IL : out STD_LOGIC);
    end mux;
    architecture Behavioral of mux is
    signal s: std_logic_vector (1 downto 0 );
    begin
    S <= S1&S0;
    with S select
    IL <= A0 when "00",
    A1 when "01",
    A2 when "10",
    A3 when "11",
    '0' when others;
    end Behavioral;

    clk div code
    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
     
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    entity clk_div is
     Port ( clk : in std_logic;
     clk2: out std_logic );
    end clk_div;
     
    architecture Behavioral of clk_div is
    begin
     
    process(clk)
     variable c : integer range 0 to 50000000:=0;
     begin
     
    if(clk'event and clk='1')then
    c:=c+1;
    if(c=50000000) then c:=0; clk2<='0';
    elsif (c=25000000) then clk2<='1';
    elsif(c<25000000) then clk2<='0';
    end if;
    end if;
    end process;
     
    end Behavioral;

    shift reg code
    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
     
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
     
    ENTITY shifter_unit is
    PORT(clk, il, ir,sin : in std_logic;
    s: in std_logic_vector (1 DOWNTO 0);
    i : in std_logic_vector (3 DOWNTO 0);
    q : out std_logic_vector (3 DOWNTO 0));
    END shifter_unit;
     
    ARCHITECTURE Behavioral of shifter_unit is
    SIGNAL qtmp : std_logic_vector(3 DOWNTO 0);
     
    BEGIN
    q<=qtmp;
    PROCESS(clk)
    BEGIN
    IF (clk = '1' AND clk'EVENT) THEN
    CASE s IS
    WHEN "00" => qtmp <= i;
    WHEN "01" => qtmp<=sin&qtmp(3 downto 1);
    WHEN "10" => qtmp<=qtmp(2 downto 0)&sin;
    WHEN "11" => qtmp<=qtmp;
    WHEN OTHERS => NULL;
    END CASE;
    END IF;
    END PROCESS;
    q <= qtmp;
    end Behavioral;

    final design
    Code VHDL - [expand]
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    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
     
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
     
    ENTITY final_design is
    PORT(clk, c : in std_logic;
    s: in std_logic_vector ( 3 DOWNTO 0);
    A : in std_logic_vector (3 DOWNTO 0);
    q : out std_logic_vector (3 DOWNTO 0));
    END final_design;
     
    architecture Behavioral of final_design is
     
    component mux is
    Port ( A0,A1,A2,A3,S0,S1 : in STD_LOGIC;
    IL : out STD_LOGIC);
    end component;
     
    component shifter_unit is
    PORT(clk, il, ir,sin : in std_logic;
    s: in std_logic_vector (1 DOWNTO 0);
    i : in std_logic_vector (3 DOWNTO 0);
    q : out std_logic_vector (3 DOWNTO 0));
    END component;
     
    component clk_div is
     Port ( clk : in std_logic;
     clk2: out std_logic );
    end component;
     
    signal il, ir, clk1 : std_logic;
     
    begin
    uo:mux port map (S(1),S(0),A(0),c,'0',A(3),il);
    u1:mux port map (S(1),S(0),A(0),c,'0',A(3),ir);
    u2:shifter_unit port map (clk1,il,ir,S(3 downto 2),A(3 downto 0),q(3 downto 0));
    u3:clk_div port map(clk,clk1);
    end Behavioral;

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  2. #2
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    Re: shift register , i have troubles when creating components please help!

    and whats the problem?



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  3. #3
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    Re: shift register , i have troubles when creating components please help!

    It doesn't look like all of your ports being assigned.


    From Final Design:

    Code:
    u2:shifter_unit port map (clk1,il,ir,S(3 downto 2),A(3 downto 0),q(3 downto 0));

    From Shift Reg Code:

    Code:
    PORT(clk, il, ir,sin : in std_logic;
    s: in std_logic_vector (1 DOWNTO 0);
    i : in std_logic_vector (3 DOWNTO 0);
    q : out std_logic_vector (3 DOWNTO 0));



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  4. #4
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    Re: shift register , i have troubles when creating components please help!

    so what should i do ?



  5. #5
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    Re: shift register , i have troubles when creating components please help!

    maybe it's supposed to be connected to a top port of final_design or generated from a component that is currently missing from the design.

    You need to learn how to ask questions if you expect more useful help. http://www.catb.org/esr/faqs/smart-questions.html



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  6. #6
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    Re: shift register , i have troubles when creating components please help!

    In situations like this, it's almost always a good idea to give the error message!



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