Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What is the purpose of using Memory Models from EDA vendor? What are its advantages ?

Status
Not open for further replies.

rshrig

Newbie level 1
Joined
Sep 30, 2010
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,291
I would like to know why do we have a Memory Models from EDA vendors(Denali , etc). What advantage does it offer compared to a behavioral memory component that can be created using verification languages?
 

How long have you spent verifying, validating and certifying what you're written, actually does what you think it does ?

Vendors are suppose to provide you with that warm fuzzy feeling.
 

I would like to know why do we have a Memory Models from EDA vendors(Denali , etc). What advantage does it offer compared to a behavioral memory component that can be created using verification languages?

what? If you are using a 3rd party IP, you DEFINITELY want to use their simulation models. If you create your own it is very easy to misinterpret things. I have used memory models that have 1k+ lines, I ceirtainly wouldn't even try to mimic them with my own code. This goes against all the reuse practices the industry is based on.
 

What advantage does it offer compared to a behavioral memory component that can be created using verification languages?
Putting it simply - Reduce dev time, cost and errors.
 

The value is in the difference between "can" and "did".
 
  • Like
Reactions: wtr

    wtr

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top