7mod998
Newbie level 4
im doing a 7-segment multiplexing code but i have error and bcd part is wrong
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; use IEEE.STD_LOGIC_arith.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sevensegment_multiplexing is Port ( clk50M : in STD_LOGIC; an : out STD_LOGIC_vector(3 downto 0); cath : out STD_LOGIC_vector(6 downto 0); bcd : in STD_LOGIC_vector(3 downto 0)); end sevensegment_multiplexing; architecture Behavioral of sevensegment_multiplexing is signal dig0,dig1,dig2,dig3:std_logic_vector(6 downto 0); signal clk1hz,clk1k:std_logic; begin clk1k_div:process(clk50M) variable c: integer range 0 to 50000; begin if(clk50M'event and clk50M='1')then c:=c+1; if(c=50000)then clk1k<='0'; c:=0; elsif(c=25000)then clk1k<='1'; elsif(c<25000)then clk1k<='0'; end if; end if; end process clk1k_div; MUX_7Seg:process(clk1k) variable S: integer range 0 to 3; begin if( clk1k'event and clk1k='1')then S:=1; Case S is when 0=>cath<=dig0; an<="1110"; when 1=>cath<=dig1; an<="1101"; when 2=>cath<=dig2; an<="1011"; when 3=>cath<=dig3; an<="0111"; end case; end if; end process MUX_7Seg ; clk1hz_div:process(clk50M) variable c: integer range 0 to 50000000; begin if (clk50M'event and clk50M='1')then c:=c+1; if(c=50000000)then clk1hZ<='0'; c:=0; elsif(c=25000000)then clk1hZ<='1'; elsif(c<25000000)then clk1hZ<='0'; end if; end if; end process clk1hz_div; process(bcd) begin case bcd is when "0000" => cath <= "0000001"; when "0001" => cath <= "1001111"; when "0010" => cath <= "0010010"; when "0011" => cath <= "0000110"; when "0100" => cath <= "1001100"; when "0101" => cath <= "0100100"; when "0110" => cath <= "0100000"; when "0111" => cath <= "0001111"; when "1000" => cath <= "0000000"; when "1001" => cath <= "0000100"; when others => cath <= "1111111"; end case; end process; cnt_1hz:process(clk1hZ) variable c: integer range 0 to 50000000; begin if(clk1hZ'event and clk1hZ='1')then c:=c+1; elsif(c=50000000)then c:=0; clk1hZ<='0'; elsif(c=25000000)then clk1hZ<='1'; elsif(c<25000000)then clk1hZ<='0'; end if; end process cnt_1hz; end Behavioral;