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  1. #1
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    How do I read a test bench input from a txt file?

    I have a txt file containing my input signal represented by 12 bit numbers in column. I need to write a test bench file that allows me to read the .txt and assign these values to a signal. I know the basic of reading from a file, but I dont really know how to make the signal update following the txt. I tried to write some loops but I couldnt make it work. I know it probably is an easy question for more expert designers, thanks to anyone willing to help

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    Re: How do I read a test bench input from a txt file?

    Do you mind to show what you already did?



  3. #3
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    Re: How do I read a test bench input from a txt file?

    Sure. I tried to adapt my usual program to work with std_logic_vector but surely I got something wrong. I cant even read the file properly atm. Signal y is declared in the architecture.

    Code VHDL - [expand]
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    --read process
     process is
        file txt_file   : text;
        variable line_v : line;
        variable slv_v  : std_logic_vector(11 downto 0);
        variable good_v : boolean;
      begin
       
        file_open(txt_file, "Input.txt", read_mode);
        readline(txt_file, line_v);
        report "line_v: " & line_v.all;
        read(line_v, slv_v, good_v);
        file_close(txt_file);
        y<=slv_v;
        wait;
      end process;



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  4. #4
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    Re: How do I read a test bench input from a txt file?

    Sure. My program looks like this atm. I didnt include initial declaration but that shouldnt be an issue, the program is compiling and executing as expected.
    Code VHDL - [expand]
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    process
               variable v_ILINE     : line;
               variable v_OLINE     : line;
               variable v_ADD_TERM1 : std_logic_vector(c_WIDTH-1 downto 0);
               variable v_ADD_TERM2 : std_logic_vector(c_WIDTH-1 downto 0);
               variable v_SPACE     : character;
                
             begin
            
               file_open(file_VECTORS, "Input.txt",  read_mode);
            
               while not endfile(file_VECTORS) loop
                 readline(file_VECTORS, v_ILINE);
                 read(v_ILINE, v_ADD_TERM1);
                 read(v_ILINE, v_SPACE);           -- read in the space character
                 read(v_ILINE, v_ADD_TERM2);
            
                 -- Pass the variable to a signal to allow the ripple-carry to use it
                 y <= v_ADD_TERM1;
                 
                  
              
               end loop;
            
               file_close(file_VECTORS);
                
               wait;
             end process

    The file looks like this, just with a lot more lines (around 2000).
    Code:
    110100010010 
    011100011001 
    010000000110 
    000001111010 
    001010100101 
    100010101010 
    111111001010 
    110011111001 
    111101011010 
    011010100101 
    111111000010 
    010110001001 
    111101111000 
    101110001111 
    111100110001 
    101010010111
    The y signal only appears to have the last line of my Input.txt file. Here I attach a quick waveform screen just for clarity. As you can see the input (y) is supposed to update but it is stuck on the 101010010111 value, which is exactly the last one in the file.



    Im sure I'm missing something thats very easy to spot but Im kind of rusty on vhdl...



  5. #5
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    Re: How do I read a test bench input from a txt file?

    In the testbench, you will need to add a wait statement. Without a wait, it will just read through the entire file and take the last one and assign it to Y, as you have found. You probably want to do something like this:

    Code VHDL - [expand]
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    while not endfile(file_VECTORS) loop
      readline(file_VECTORS, v_ILINE);
      read(v_ILINE, v_ADD_TERM1);
      read(v_ILINE, v_SPACE);           -- read in the space character
      read(v_ILINE, v_ADD_TERM2);
            
      -- Pass the variable to a signal to allow the ripple-carry to use it
      y <= v_ADD_TERM1;
      wait until rising_edge(clk_out1);          
    end loop;



  6. #6
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    Re: How do I read a test bench input from a txt file?

    First try what #5 - TrickyDicky recommends.

    Secondly, when dealing with reading of files you may want to inspect the different types of libraries available to you. Some will enable the reading & writing of binary, others will allow hex, dec etc.

    Overall it looks like you're logic is sound



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  7. #7
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    Re: How do I read a test bench input from a txt file?

    At one time I had to do a lot of this, and we found the best
    way was to use external scripts (I started with sed -e, then
    a CAD lady turned it into cleaner perl scripts for ut) to add
    veriloga header, massage vectors (we had timestamp and
    value, not just value - you need to assign that somehow)
    and veriloga footer, stuff that to underneath a "testVectors"
    symbol/veriloga pair as its verilog.va view, and badda-bing,
    a pattern generator for schematic based mixed signal.



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