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    Layout of Transistors with large width and large current draw

    Hello,

    I am laying out a CMOS transistor (with fingered layout) of a quite wide transistor (width = 500um, length = minimum) for high speed mmwave application.

    The transistor is not in the RF path and is in the DC path and is drawing 20mA of current.

    I have heard of something called vertical layout where you connect transistors vertically with the gate connections vertically applied.

    My question: how do I lay out this large width transistor while meeting metal current density rules and what is the proper finger widths and segmentation of the width to meet reliability, and again metal current density rules and have easy routing for the interconnect/signals ?

    Thanks.

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    Re: Layout of Transistors with large width and large current draw

    20mA is not a lot of current. But it may be a lot of current
    density if you use minimum interconnect (as the library PCell
    will probably present to you).

    Figure roughly 1mA/um (read your PDK EM rules document for
    the actual) this wants a minimum of 20um width in the metal.

    You need to think about where the current comes from and
    goes, on what "natural" routing level. You will drop down from
    there to Met1 by a series of vias and local routes, and all of
    these need to meet EM rules as well.

    If this transistor has no high speed / frequency requirements
    then I would leave the gate routing for last. You can stub out
    the poly for a few microns.

    If this transistor is connected to a pad then it should follow
    ESD rules. These often include a silicide blocked "pullback"
    region, in whcih you can fit extra metal with no penalty.
    Do this first and see what metal width a finger can have.
    Then, see how much current that can "legally" support.
    Then divide your 20mA by this, and there's your minimum
    finger count.

    You may still be better off with more, narrower fingers.
    May want to break up the device into 2, 4, ... "beds"
    and route the main metal interdigitated over them all at
    half the active width (less spacing), dropping down
    through vias to the S/D. Maybe this is what you call
    "vertical layout", I dunno. But I have laid out many a
    power stage in this sort of way. Usually with some cross
    strapping between the segments in the mid levels, just
    for luck / balance.



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    Re: Layout of Transistors with large width and large current draw

    500um is huge for 20mA if this MOS has not intentionally been used in a special form..
    If we consider the tech. min. length is 0.1um, the ratio is 5000 !! It looks weird for 20mA.
    I used a RFCMOS for a symmetrical LNA that drew 7mA of each tail, the dimensions are 18/0.25 um.
    OK, the technology is different but it still looks strange..



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    Re: Layout of Transistors with large width and large current draw

    Hello,

    This transistor is in the DC path of a very high speed broadband amplifier (mmwave) and not in the RF path.

    It is mainly used for biasing/broadband matching. I realize it is huge.

    Since in the DC path I dont think it will affect the high frequency performance since its not in the RF path.

    I am just concerned about routing the interconnect to meet current density requirements and making sure the transistor (there is only one here) is laid out properly to also meet the current density requirements of the transistor.



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