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CMOS current reference with beta multiplier and inverse widlar current source

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deveshkm

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View attachment CMOS_CURRENTREFERENCE_13PPM (1).pdf

Hi, I have referred this paper for designing current reference.

But, I have not used cascode transistors (like PMOS cascode shown in the reference)

I obtained a temperature coefficient of 650 ppm /C.

The major concern is that some transistors entered linear or cutoff region at few points in the plot versus temperature.
However, the generated current ( temp co 650 ppm) ensured that transistors in the main amplifier remained in saturation

What impact will this have on the chip?
 

When you get a temperature coefficient of 650ppm/degC, is this across PVT corners or only at a particular Process and Voltage?

Some Schematics/design details would be of help.
 

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