Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Cadence Genus Synthesis] How to add more than one library file for synthesis?

Status
Not open for further replies.

kurax

Newbie level 4
Joined
Mar 26, 2017
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
50
My Synthesis Script,

Code:
#Setting Library and Design Path
set_attribute lib_search_path ../lib/
set_attribute hdl_search_path ../design_files/

#Setting Library and Design Files
set_attribute library tech.lib

#Analyze and Elaborate the Design File
read_hdl -sv counter.sv
elaborate

# Apply Constraints and generate clocks
read_sdc ../constraints/constraints.sdc

# Synthesize the design to the target library
synthesize -to_mapped -effort medium

# Write out the reports
report timing > counter_timing.rep
report gates  > counter_cell.rep
report power  > counter_power.rep

# Write out the structural Verilog and sdc files
write_hdl > counter_netlist.v
write_sdc > counter_sdc.sdc


This is the script I use to synthesize my design file. My question is, I want to use multiple library files. Say tech1.lib, tech2.lib, etc. Use the synthesis tool to take in all of them and do synthesis for each and every one of them and generate reports. And if possible the synthesis tools should automatically say which library best matches the timing.

Thanks in advance.
 

My Synthesis Script,

Code:
#Setting Library and Design Path
set_attribute lib_search_path ../lib/
set_attribute hdl_search_path ../design_files/

#Setting Library and Design Files
set_attribute library tech.lib

#Analyze and Elaborate the Design File
read_hdl -sv counter.sv
elaborate

# Apply Constraints and generate clocks
read_sdc ../constraints/constraints.sdc

# Synthesize the design to the target library
synthesize -to_mapped -effort medium

# Write out the reports
report timing > counter_timing.rep
report gates  > counter_cell.rep
report power  > counter_power.rep

# Write out the structural Verilog and sdc files
write_hdl > counter_netlist.v
write_sdc > counter_sdc.sdc


This is the script I use to synthesize my design file. My question is, I want to use multiple library files. Say tech1.lib, tech2.lib, etc. Use the synthesis tool to take in all of them and do synthesis for each and every one of them and generate reports. And if possible the synthesis tools should automatically say which library best matches the timing.

Thanks in advance.

Code:
set LIB_NAME1 lib1.lib
set LIB_NAME2 lib2.lib

set_db / .library "$LIB_NAME1 $LIB_NAME2"
 

Code:
set LIB_NAME1 lib1.lib
set LIB_NAME2 lib2.lib

set_db / .library "$LIB_NAME1 $LIB_NAME2"


Thanks. But this looks like it takes multiple library files. But how to write multiple reports. I was guessing, we should use variables names at the end of the report files, like counter_timing_$LIB_NAME1.rep. Also does it take care of choosing the best library?
 

Thanks. But this looks like it takes multiple library files. But how to write multiple reports. I was guessing, we should use variables names at the end of the report files, like counter_timing_$LIB_NAME1.rep. Also does it take care of choosing the best library?

What you are asking is for the tool to do your job as a designer. That won't happen. Just run synthesis twice with different libs and compare the results. This isn't rocket science.
 

What you are asking is for the tool to do your job as a designer. That won't happen. Just run synthesis twice with different libs and compare the results. This isn't rocket science.

That's what I wanted to know.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top