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Is logic cell a technology independent parameter

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rafimiet

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I want to compare the logic resources utilized by my design with other designs. But the previous designs are implemented on other FPGA boards. It is very obvious that I can not compare LUTs because my FPGA board uses 6-input LUT and their FPGA uses 4-input LUT. I have heard that logic cell count is independent of technology. Can I compare the designs on basis of logic cells??
 

Not sure where you heard that. A logic cell is basically a lut.
 

I think logic resources utilized by the design depends on 2 things

1. the FPGA used for design

2. the IDE used to implement the design as different IDE tools uses different optimization algorithms.
 

It is very obvious that I can not compare LUTs because my FPGA board uses 6-input LUT and their FPGA uses 4-input LUT.
How/why do a say that?

A typical Xilinx 7 series FPGA contains LUT* = Primitive: *-Bit Look-Up Table with General Output (* can be 2,3,4,5,6)
The LUT* is generated by the tool depending on the logic synthesized.

Take a look at the runme.log of the synth projects to get an idea.
 

I want to compare the logic resources utilized by my design with other designs. But the previous designs are implemented on other FPGA boards. It is very obvious that I can not compare LUTs because my FPGA board uses 6-input LUT and their FPGA uses 4-input LUT. I have heard that logic cell count is independent of technology. Can I compare the designs on basis of logic cells??

That is a pretty common problem, actually. If you want to compare two designs, you can use number of NAND2 equivalent gates or some metric like that. You don't even need an FPGA for that. Think of your design as an ASIC, just count gates.
If you want to compare two implementations on different FPGAs, number of LUTs is the most simple way of doing it. The caveat of course is that LUTs vary from family/vendor. You can't get a fair comparison based on LUTs alone.
 

A logic cell is basically a lut.
I don't think so... Had it been so then in the devices XC6VLX240T should have had 150720 number of logic cells as it contains 150720 number of LUTs, but it has 241152 number of logic cells!!!

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How/why do a say that?

A typical Xilinx 7 series FPGA contains LUT* = Primitive: *-Bit Look-Up Table with General Output (* can be 2,3,4,5,6)
The LUT* is generated by the tool depending on the logic synthesized.

Take a look at the runme.log of the synth projects to get an idea.

I did not understand a word here, please explain a bit more...
 

I don't think so... Had it been so then in the devices XC6VLX240T should have had 150720 number of logic cells as it contains 150720 number of LUTs, but it has 241152 number of logic cells!!!

Logic cells for V6 and V7 is a BS number that was added to help users compare/understand the difference between the 6-input v.s. 4-input LUT. When Xilinx came out with V5 they didn't have that BS number and they had a bunch of problems with people thinking the parts were smaller than they were (CLB counts were smaller than the claimed size of the part, in terms of the 4-input LUT that everyone was familiar with).

The factor for the Logic cells to LUTs is a 1.6 factor for both V6 & V7, which is supposed to imply that you can fit approximately 1.6 LUTs worth of logic in the 6-input LUT compared to a 4-input LUT, though YMMV ;-).

I would focus on just the number of slices and ignore the BS logic cell numbers (with the understanding that V5 has 4-LUTs 4-FFs in a slice and V6 & V7 both have 4-LUTs and 8-FFs in a slice).
 
The factor for the Logic cells to LUTs is a 1.6 factor for both V6 & V7, which is supposed to imply that you can fit approximately 1.6 LUTs worth of logic in the 6-input LUT compared to a 4-input LUT, though YMMV ;-).
This was really a great help. The only confusion I have now is that: Why the devices based on 4-input LUTs (like Virtex-4) have a "no. of cells/no. of LUTs" ratio of 1.125?
 

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