E
expertengr
Guest
Hello,
RTL is synthesizeable while Behavioral is not synthesizeable because it contain loops, wait statements. Is this statement true ? What about if Behavioral does not contain loops and wait statements ? The following example is synthesizeable and represents Behavioral modeling.
entity half_adder is
architecture behavior of half_adder is
I am wondering what is the main difference between Behavioral, RTL, Structural and Gate Level in VHDL. Could anyone share example of each ? There are some posts regarding this issue but they are old and I don't know if is there any change in definition or concepts over the years ? because there are some tools which can synthesize loops. Where can I find VHDL - 2008 user guide ?
RTL is synthesizeable while Behavioral is not synthesizeable because it contain loops, wait statements. Is this statement true ? What about if Behavioral does not contain loops and wait statements ? The following example is synthesizeable and represents Behavioral modeling.
entity half_adder is
Code:
port (a, b: in std_logic;
sum, carry_out: out std_logic);
end half_adder;
architecture behavior of half_adder is
Code:
begin
ha: process (a, b)
begin
if a = ‘1’ then
sum <= not b;
carry_out <= b;
else
sum <= b;
carry_out <= ‘0’;
end if;
end process ha;
end behavior;
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