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Behavioral, RTL, Structural and Gate Level - how to differentiate them in VHDL

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expertengr

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Hello,

RTL is synthesizeable while Behavioral is not synthesizeable because it contain loops, wait statements. Is this statement true ? What about if Behavioral does not contain loops and wait statements ? The following example is synthesizeable and represents Behavioral modeling.

entity half_adder is
Code: 
  port (a, b: in std_logic;
    sum, carry_out: out std_logic); 
  end half_adder;

architecture behavior of half_adder is
Code: 
  begin
    ha: process (a, b)
    begin
      if a = ‘1’ then
        sum <= not b;
        carry_out <= b;
      else
        sum <= b;
        carry_out <= ‘0’; 
      end if;
    end process ha;

end behavior;
I am wondering what is the main difference between Behavioral, RTL, Structural and Gate Level in VHDL. Could anyone share example of each ? There are some posts regarding this issue but they are old and I don't know if is there any change in definition or concepts over the years ? because there are some tools which can synthesize loops. Where can I find VHDL - 2008 user guide ?
 
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These terms are not accurate. There is a synthesizable subset of VHDL (and Verilog).

Your code seems to be a behavioral description within a module used for structural modeling.
 

vGoodtimes said:
These terms are not accurate. There is a synthesizable subset of VHDL (and Verilog).

Your code seems to be a behavioral description within a module used for structural modeling.
Click to expand...

Is there any reference document which describe these terms for VHDL 2008 ?
 

RTL, Behavioural and Structural terms are not connected directly to VHDL. RTL has generally become a term to mean synthesisable HDL. But RTL code can contain behavioural features (Inference of RAMs, DSP etc).
Strutural generally means HDL full of entity instantiations. But usually it goes alongside some RTL in the same file too.

RTL, Behavioural and Structoral are not mutually exclusive things. In the past, they may have been when synthesis tools were not so good at understanding HDL, and were less flexible in the code they allowed - And these idea remains. But now these terms are mostly redundant. Most people just refer to "synthesisable" and "non-synthesisable" code. The subset that is synthesisable continues to grow.

Gate Level generally refers to simulation of a netlist (not written by a human - unless you're a masochist)

I would describe the code you posted as RTL. If it contained loops and was still synthesisable I would still call it RTL.

- - - Updated - - -

Decent guides on the changes for VHDL 2008 are here:
https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/

and a webinar here:
https://www.doulos.com/content/events/VHDL_2008.php
 

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