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Need logic that implement in Verilog coding

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tayyab786

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There are seven d/f inputs from seven different module are received by one module..an array have some value is already present in the that module.

Now the first index value of array is assign to those module which has largest input value... and 2nd index value of array are assign to those module which has 2nd largest value and so on. it is also possible that two, or more than two input have same value. in this case system, separate those input value and not assign any index value of array.. so at last we also know that which input has same value..

I know some logic's but the the problem is, it require to many iteration. which is not desired.



Thanks in advance and ignore my english
 

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