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Want to convert 32 bit data into 4 group of 8 bit data for UART

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Krishna_k

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[Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

Hello,

I want to send 32 bit data (which is continuously coming from filter) through UART transmitter. I think I have to use block RAM with shift register. Can any on help me with this?
I want some examples how to do this in VHDL. my platform is Sparten 3E FPGA and use xilinx 14.5 for programming.
 

Re: how to synchronize 32bit (live) data with UART on spartan 3E.

Hi,

What is the problem?
It's not clear to me.

What do you mean with:
* synchronize, live
* coming from filter

I recommend to add a draft to explain the problem.

Klaus
 

Re: how to synchronize 32bit (live) data with UART on spartan 3E.

You question is incomplete and missing details!

Send 8 bits via UART at a time (you have not mentioned what is the destination), avoid sendind data > 8bits via uART.
32bits i/p --> FIFO --> 8bits output --> shift reg --> UART tx --> destination (UARt rx)

I want some examples how to do this in VHDL.
Use a search engine, lots of VHDL eg are available.
 

Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

Hello,

I want to send 32 bit data (which is continuously coming from filter) through UART transmitter. I think I have to use block RAM with shift register. Can any on help me with this?
I want some examples how to do this in VHDL. my platform is Sparten 3E FPGA and use xilinx 14.5 for programming.

how is the data coming? Is it axi protocol compatible? If yes then I suggest you go through the below link. You can find examples. Show us the code which tells about the function of filter.

https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf
 

Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

Thanks all for replying

I designed a digital filter,it gives 32 bit output. I want to tak that output in my laptop let's say in hyper terminal. So I make a code for UART which support 8 bit transmission at a time.
I need to transmit 32 bits so I make a loop to divide 32 bits in 4 8bit grops but its not working.
N second thing filter gives output on 220KHZ frequency. UART baud rate is 115200. Clearly I need memory. I decide to use block ram in fpga.

So my question is what size of memory may I need for this?
And how can I divide my 32 bits in 4 groups of 8 bit?
 

Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

Hi,

I see a lot of issues:
* If the filter_out frequency is 220kHz, you need a baudrate of at least 220kHz x 4 (bytes) x 10 (bits per byte) = 8,8MBaud (simple math, btw)
* Just shifting 32 bits out won't work.
* You need to include STARTBITs and STOPBITs.
* And you need some kind of framesync. Either by timing or by data
* Also you need a RS232 level converter
* And you have to consider that Hyperterminal may have problems to binary data.

Klaus
 

Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

So my question is what size of memory may I need for this?
And how can I divide my 32 bits in 4 groups of 8 bit?

The model I proposed in #3 should still be good.

I think you should study more about FIFOs first, before you work on the transmit part of your data via UART.
https://www.xilinx.com/support/docu...fifo_generator/v13_1/pg057-fifo-generator.pdf

Study about dual clock FIFO with native interface in the above document (use a BRAM for the FIFO implementation ). A FIFO memory can be generated using Vivado as an IP core which you can instantiate inside your design between the filter and the UART modules.

FIFO write i/f could be with 220KHz clk (which is a relatively slow clock) with the write port width being 32 bits an the read port (interfacing with the UART) can be 8 bits.
 
Last edited:

Re: [Moved] how to synchronize 32bit (live) data with UART on spartan 3E.

Your filter outputs 32 Bit data at 220 kHz rate. This is about 7 Mbit/s, no chance to transmit it continuously through 115 kBit/s UART. A FIFO allows to store a short block of filter output data and replay it at lower speed. Is this what you want?
 

hello

I am making a UART transmitter which send data from FPGA sparten 3E to PC. here the problem is The size of the data is 32 bit. UART have limitation to send 8 bit data. I am converting 32 bit into 8 bits and give it to uart transmitter. It gives output but the order of the output is in reserves.
I don't understand how it is happening. Can anyone help me in this? I provide my code below.
Code:
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:29:42 03/20/2018 
-- Design Name: 
-- Module Name:    uartTop - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library work;
--use work.uart2BusTop_pkg.all;

entity uartTop is
  port ( -- global signals
         clr       : in  std_logic;                     -- global reset input
         clk       : in  std_logic;                     -- global clock input
         serOut    : out std_logic;                     -- serial data output
         newTxData : in  std_logic;                     -- asserted to indicate that there is a new data byte for transmission
         txBusy    : out std_logic;                     -- signs that transmitter is busy
         
			baudClk   : out std_logic);                    -- 
			
end uartTop;

architecture Behavioral of uartTop is

  signal ce16 : std_logic; -- clock enable at bit rate
  signal Data: std_logic_vector(7 downto 0);
  signal Data1: std_logic_vector(31 downto 0);
  signal i: integer range 0 to 3:= 0;
  signal slow_clock : std_logic;
  
component baudGen
    port (
      clr       : in  std_logic;
      clk       : in  std_logic;
     slow_clock : out  std_logic;
      ce16      : out std_logic);
  end component;

  component uartTx
    port (
      clr : in  std_logic;
      clk : in  std_logic;
      ce16 : in  std_logic;
      txData : in  std_logic_vector(7 downto 0);
      newTxData : in  std_logic;
      serOut : out  std_logic;
      txBusy : out  std_logic);
  end component;


  begin
    -- baud rate generator module
    bg : baudGen
      port map (
        clr => clr,
        clk => clk,
		slow_clock => slow_clock,
        ce16 => ce16);
    -- uart receiver
    ut : uartTx
      port map (
        clr => clr,
        clk => clk,
        ce16 => ce16,
        txData => Data,
        newTxData => newTxData,
        serOut => serOut,
        txBusy => txBusy);
    baudClk <= ce16;

	
process (slow_clock)
variable i : integer range 0 to 3 := 0;
	
begin 
	if (rising_edge(slow_clock)) then
			if i = 0 then 
			Data<= Data1(31 downto 24);
			i := 1;
			
			elsif i = 1 then
			Data<= Data1(15 downto 8);
			i := 2;
			
			elsif i = 2 then
			Data<= Data1(23 downto 16);
			i := 3;
		
			elsif i = 3 then
			Data<= Data1(7 downto 0);
			i := 0;
			
			end if;
 end if;
end process;
	 

Data1<= "00110000001100010011001000110011"; --00110000 = 0,00110001= 1,00110010= 2,00110011= 3 

	
end Behavioral;
 

Do you really mean to send bits 15-8 (i=1) before sending bits 23-16 (i=2)? Should they be swapped?
 

Apart from possibly confused byte order, the scheduling logic doesn't seem to make sense. The mux state machine is triggered by an internal generated slow_clock, but UART transmission started by external signal nexTxData.

I would expect a state machine advanced when UART signals end of previous transmission.
 

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