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[SOLVED] Modelsim do not provide output for module with delay more than 1ns

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Anklon

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Modelsim do not provide output for module with delay more then 1ns

I'm trying to delay ripple clock where output of D-flipflop will go through a delay cell before reaching another D-flipflop. If I use delay cell with 1ns delay, Modelsim simulate it fine.
Code: 
`timescale 1ns/10ps

module CLKDLY2X1(A,Z);
input A;
output Z; 

assign #1  Z = A;
endmodule
Here is the output (output simulation window 40ns):
1ns.PNG

If I change the delay into 2ns or more, delay cell do not give any output though it compiles with zero warning.
Code: 
`timescale 1ns/10ps

module CLKDLY2X1(A,Z);
input A;
output Z; 

assign #2  Z = A;
endmodule
2ns.PNG

Is there any such kind of limitation in modelsim or I'm doing some silly mistakes ?
Thank You for your time.
 

Re: Modelsim do not provide output for module with delay more then 1ns

The behavior is correct according to Verilog language reference. Delay is larger than pulse duration.
 

Re: Modelsim do not provide output for module with delay more then 1ns

Why pulse duration have to be larger then Delay ? suppose I want to give a 1ns pule at one node and want to send the same pulse at different node with with 2n delay, it is physically possible to design a 2ns delay block manually. Now I wanna use that block as module to simulate Verilog, what should I do ?
 

Re: Modelsim do not provide output for module with delay more then 1ns

The continuous assign statement and gate primitives simulate using an inertial delay model. That means the output cannot change faster than the input. You want a transport delay model. For that you need to use specify block path delays, or the non-blocking assignment. Specify blocks can get quite involved, so I'll just show the non-blocking assignment version:
Code Verilog - [expand]
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`timescale 1ns/10ps
 
module CLKDLY2X1(input  wire A,
                 output reg  Z); 
 
  always @A Z <= #2 A;
endmodule
 
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    Anklon

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