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Verilog - ignored specified memory location

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crystal

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I'm exploring some testing in memory field.

Let say I have identified that the memory at this address location (i.e addr=4'b0010) is faulty and I would like to 'mark' it, ignore it when it's writing operation on the memory. It should be able to go to the next location (i.e addr=4'0011) which is not faulty.
Can this be done using Verilog codes? Any idea or suggestion?
 

Do you mean you just want to write a pattern(testbench) to test the MEM READ/WT?
if yes, at this pattern, the RAM for you is only a model,you can add a if~else statement in this model to restrict write to address (0010),(it's only a model, so physical error is not importment, what you want to test is the rd/wt waveform, so I dont think you need fix the model, just think 0010 is OK).
if you are in max product test, just fix the pattern (if add=0010 , don't write/read...)!
 

hi crystal,
As I know, the thing you want to is Built-In Self Repair relative circuits.
You can search BISR(built-in self repair) in google to get the information about this.
I had read a thesis of this topic, he claim he implement and simulation the circuit in VHDL.

Regards,

Jarod
 

If you implement the write address using a counter and you know which are the faulty addresses, then the counter at that point will increment by 2 and not 1 as in normal case.
So if you know that the 4'b0010 should not be accessed, when the counter is in 4'b0001 it should be incremented by 2 and go to 4'b0011.
 

hi jarodz,
You are right that i'm looking at BISR. The papers that i've seen mentioned about this being done with automatic repair or rather online.

What i'm interested on is offline - meaning being able to identify where's the faulty location of address & automatically being ignored. Each time, it might be different address which is faulty.
 

hi crystal,
I am sorry that I have fogot this post.
I don't understand clearly what you describe?
The meaning of online/offline?
Or this probelm is solved?
If it is, can you share your solution to me.
Thanks.

Regards,
Jarod
 

jarodz said:
hi crystal,
As I know, the thing you want to is Built-In Self Repair relative circuits.
You can search BISR(built-in self repair) in google to get the information about this.
I had read a thesis of this topic, he claim he implement and simulation the circuit in VHDL.

Regards,

Jarod
Click to expand...



Hi jarodz
I need some books or thesis on BISR.could you please send me if you have one.

my email:payamhabiby@yahoo.com

Best regards
 

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