Clock tree synthesis

What is skew and how to identify the skew either clock signal to clock signal or clock signal to data signal or data signal to data signal?

Clock skew is the time difference in arrival of same clock signal at different components of a synchronous design, due to delays being added in clock path.

Clock skew means time difference between two clock input of two different cell from same clock source. Due to different wire length, clock skew occurs.Fan-out from the clock source may also have an effect.
It's not something you should concern or can detect in small circuits. But it's a must concern in complicated circuits where you have to supply same clock signal to a lot of synchronous cell. To see it, you should take layout of a complete synchronous circuit (make sure it's wire connections are lengthy enough that it's resistance become considerable) without clock tree synthesis (clock tree synthesis resolve clock skew problem). then find smallest and longest wire that go out from clock source. find out their time difference of clock arrival at the ending point. (buffer cells should be considered too as they also induce time delay of the line)

some misconceptions have to be clarified

"Due to different wire length, clock skew occurs" clock skew has many sources, not only wire length.
"make sure it's wire connections are lengthy enough that it's resistance become considerable" this is not needed.
"clock tree synthesis resolve clock skew problem" MODERN clock tree synthesis does not resolve clock skew problem, it leverages clock skew into useful skew. big difference.
"then find smallest and longest wire that go out from clock source" to what end?