varthurravi
Newbie level 5
Hi,
I have a Xilinx Zynq-based FPGA design that I am running timing simulation on.
RTL Simulation --- passes
Post P&R GLS (Without SDF) --- Passes
Post P&R GLS (With SDF) --- Fails (All outputs/registers stuck at 0)
Any clue what could cause this?
There are no timing violations in the simulation or P&R reports.
I have the timescale set to 100ps/1ps in TB and in all modules.
I have a 100ns delay inserted to take care of Xilinx GSR requirements.
The clock is running at 25 ns.
Thanks
RV
I have a Xilinx Zynq-based FPGA design that I am running timing simulation on.
RTL Simulation --- passes
Post P&R GLS (Without SDF) --- Passes
Post P&R GLS (With SDF) --- Fails (All outputs/registers stuck at 0)
Any clue what could cause this?
There are no timing violations in the simulation or P&R reports.
I have the timescale set to 100ps/1ps in TB and in all modules.
I have a 100ns delay inserted to take care of Xilinx GSR requirements.
The clock is running at 25 ns.
Thanks
RV