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  1. #1
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    GLS (Timing Simulation) Issue

    Hi,

    I have a Xilinx Zynq-based FPGA design that I am running timing simulation on.

    RTL Simulation --- passes
    Post P&R GLS (Without SDF) --- Passes
    Post P&R GLS (With SDF) --- Fails (All outputs/registers stuck at 0)

    Any clue what could cause this?

    There are no timing violations in the simulation or P&R reports.
    I have the timescale set to 100ps/1ps in TB and in all modules.
    I have a 100ns delay inserted to take care of Xilinx GSR requirements.
    The clock is running at 25 ns.

    Thanks
    RV

    •   Alt13th March 2018, 16:02

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  2. #2
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    Re: GLS (Timing Simulation) Issue

    Do like the rest of us do...Debug the simulation.

    Start with the fault and trace back to the cause of the fault. You may have to look at the signals inside the simulation primitives as it's likely you still have GSR problems in the simulation.



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