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AXI4 to AXI Stream conversion for Ultrascale PCIe EP support

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sreevenkjan

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Hi all,

I am building a PCIE EP using Ultrascale PCIe IP from Xilinx. I am using 2017.3 Vivado for the design.
Since the ultrascale EP supports only AXI Stream, I need a converter from AXI4 to AXIS, I went through some of the forums and read that people could use AXI-DMA or AXI-Datamover IP to handle both AXI4 to AXIS.

My question is do I need to use a DMA or a Datamover, the PCIe EP would be programmed in a hardware board and would act as a streaming endpoint. Which IP would be suited in this case?

Thanks for your help.

regards,
Sreeni
 

Any Idea guys, I would like to have it bidirectional. That is from host to system and viceversa.

Let me frame my question in a different way. Do we need to program DMA/Datamover if I use them in my design? I could generate a block design and get it synthesized but do I need to program the DMA to send the data from AXI4 source to AXI-Stream PCIe EP??

Thanks,
Sreeni
 

What is your use case? Both IPs are able to move data from memory mapped to streaming (and vice versa) - the AXI-DMA requires a master in the design, which configures the DMA by writing to registers, the DataMover has a streaming interface for control. In any case we need more information regarding your use case, since there are many ways to handle such things. Another thing: Are you sure, that the PCIe IP isn't able to act as an AXI-MM master/slave? Last year I used the PCIe DMA-Subsystem IP and it worked totally fine (for Virtex 7).
 

What is your use case? Both IPs are able to move data from memory mapped to streaming (and vice versa) - the AXI-DMA requires a master in the design, which configures the DMA by writing to registers, the DataMover has a streaming interface for control. In any case we need more information regarding your use case, since there are many ways to handle such things. Another thing: Are you sure, that the PCIe IP isn't able to act as an AXI-MM master/slave? Last year I used the PCIe DMA-Subsystem IP and it worked totally fine (for Virtex 7).


I decided to use AXI Stream FIFO and AXI Datamover. AXI Stream FIFO would be from MM Master to streaming slave and from Streaming slave to MM slave I would use AXI Datamover. Yes you are right the AXI Datamover uses streaming interface for control i.e for sending address commands. The Ultrascale FPGA Gen3 IP block does not have AXI4-MM Master/slave ports. It has requestor and completer interface which are streaming interfaces.

Do you think the above mentioned configuration would work? I was planning on writing my own logic for the datamover streaming command signals so that the address would be delivered to the right slave on the receiving side..
 

Do you think the above mentioned configuration would work? I was planning on writing my own logic for the datamover streaming command signals so that the address would be delivered to the right slave on the receiving side..

I'm still not sure, what purpose your design will have - but here is my generic recommendation: Use the DMA/PCIe combo (https://www.xilinx.com/support/documentation/ip_documentation/xdma/v4_0/pg195-pcie-dma.pdf) if you want to have a simple PCIe to AXI-MM adapter. I used it in my accelerator card with Linux and it worked quite nice. If you want to handle requests and completes on your own, then develop your own logic, which translates PCIe relevant data to AXI-MM data. Please give us some more design information, if you need more help.
 

well I want to build a hardware with PCIe Stream IP (Ultrascale PCIe IP), I have a AXI MM source. So I send my AXI MM signals to AXI Stream FIFO and then to PCIe Stream IP.
on the other side I have AXI Datamover which receives signals from PCIe IP and then does the AXI Stream to AXI MM conversion and send it to my AXI MM Slave. I want to have a AXI Stream to AXI MM conversion. Since my PCIe EP handles only AXI Stream signals, I need to convert the AXI MM signals from my source and send it to my AXI Stream PCIe EP.
 

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