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  1. #1
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    Shift register bitwidth issue

    Why do RD_DATA and wDataShift need bitwidth of "[(C_DEPTH+1)*C_WIDTH-1:0]" in the following "shift register" module ?


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    // ----------------------------------------------------------------------
    // Copyright (c) 2016, The Regents of the University of California All
    // rights reserved.
    // 
    // Redistribution and use in source and binary forms, with or without
    // modification, are permitted provided that the following conditions are
    // met:
    // 
    //     * Redistributions of source code must retain the above copyright
    //       notice, this list of conditions and the following disclaimer.
    // 
    //     * Redistributions in binary form must reproduce the above
    //       copyright notice, this list of conditions and the following
    //       disclaimer in the documentation and/or other materials provided
    //       with the distribution.
    // 
    //     * Neither the name of The Regents of the University of California
    //       nor the names of its contributors may be used to endorse or
    //       promote products derived from this software without specific
    //       prior written permission.
    // 
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
    // UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
    // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    // BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    // OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    // ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
    // TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
    // USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
    // DAMAGE.
    // ----------------------------------------------------------------------
    /*
     Filename: shiftreg.v
     Version: 1.0
     Verilog Standard: Verilog-2001
     
     Description: A simple parameterized shift register. 
     
     Notes: Any modifications to this file should meet the conditions set
     forth in the "Trellis Style Guide"
     
     Author: Dustin Richmond (@darichmond) 
     Co-Authors:
     */
    `timescale 1ns/1ns
    module shiftreg
        #(parameter C_DEPTH=10,
          parameter C_WIDTH=32,
          parameter C_VALUE=0
          )
        (input                            CLK,
         input                            RST_IN,
         input [C_WIDTH-1:0]              WR_DATA,
         output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
     
        // Start Flag Shift Register. Data enables are derived from the 
        // taps on this shift register.
     
        wire [(C_DEPTH+1)*C_WIDTH-1:0]    wDataShift;
        reg [C_WIDTH-1:0]                 rDataShift[C_DEPTH:0];
     
        assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
        always @(posedge CLK) begin
            rDataShift[0] <= WR_DATA;
        end
        
        genvar                                     i;
        generate
            for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
                assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
                always @(posedge CLK) begin
                    if(RST_IN)
                        rDataShift[i] <= C_VALUE;
                    else
                        rDataShift[i] <= rDataShift[i-1];
                end
            end
        endgenerate
        assign RD_DATA = wDataShift;
        
    endmodule

    •   Alt13th March 2018, 04:15

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  2. #2
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    Re: Shift register bitwidth issue

    Did you understand the purpose of the module at all? Apparently the module exposes all shift register taps.


    1 members found this post helpful.

    •   Alt13th March 2018, 07:49

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  3. #3
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    Re: Shift register bitwidth issue

    exposes all shift register taps.
    I am sorry, but I do not understand the purpose of the module.

    I could not comprehend why the author needs such bitwidth for RD_DATA and wDataShift



    •   Alt13th March 2018, 12:03

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  4. #4
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    Re: Shift register bitwidth issue

    I don't understand the word "issue" in the thread title.

    You don't use the code for a specific purpose, you neither can't imagine a possible purpose, why bother with it at all?



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    Re: Shift register bitwidth issue

    Quote Originally Posted by promach View Post
    I am sorry, but I do not understand the purpose of the module.

    I could not comprehend why the author needs such bitwidth for RD_DATA and wDataShift
    They don't they just decided to expose all the shift register taps.

    The purpose of the module is clearly stated in the header (did you read it)
    Code:
    Description: A simple parameterized shift register.
    - - - Updated - - -

    Or perhaps you are making a case for the poorly written code that does something different than what is inferred by the parameters.

    Code:
    parameter C_DEPTH=10,
    parameter C_WIDTH=32,
    That implies the shift register has 10 pipeline stages and is 32-bits wide, i.e. 10*32 = 320 FFs e.g. output [319:0] RD_DATA;

    The output (and the shift register definitions) imply the depth is 11.
    Code:
    output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
    ((10+1)*32)-1 = 351

    I'm not overly impressed by the code you've been getting from "The Regents of the University of California". This particular example is really bad IMO.
    Last edited by ads-ee; 13th March 2018 at 16:01. Reason: fix double post due to website problems


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  6. #6
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    Re: Shift register bitwidth issue

    // Start Flag Shift Register. Data enables are derived from the
    // taps on this shift register.
    Could anyone elaborate on the comments ?



    •   Alt15th March 2018, 13:13

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  7. #7
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    Re: Shift register bitwidth issue

    It has already been told to you by FVM on #2.

    Click image for larger version. 

Name:	sr.jpg 
Views:	3 
Size:	14.2 KB 
ID:	145366

    Q1, Q2, Q3, Q4 are called the shift-reg taps. So wrt your query, Q1 is one enable, Q2 is another enable, and so on.

    Note: I didn't look into the RTL you posted in #1.
    .....yes, I do this for fun!



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