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  1. #1
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    Calibre PEX simulation results

    ok back again, after seemingly getting Calibre DRC, LVS to work, I ran PEX. It gave me no errors but when I simulate the testbench with the calibre PEX view, my waveforms don't look right. The circuit is an example one, ( 2 stage buffer), from the TSMC flow guide.

    I am using calibre from the cadence environment and in my view setup file have view type as maskLayout and create terminals if matching terminals exist on symbol.
    I am getting two warnings

    WARNING: [FDI3022] Not creating terminal VDD! in (buffer2 calibre) since matching terminal was not found on symbol.
    WARNING: [FDI3022] Not creating terminal GND! in (buffer2 calibre) since matching terminal was not found on symbol.
    Calibre View generation completed with 2 WARNINGs and 0 ERRORs. Please consult the CIW transcript for messages

    I didn't create a VDD and GND pin in my symbol view even though the schematic cell view below have those nets.


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  2. #2
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    Re: Calibre PEX simulation results

    If you use Inherited Connections in layout, you should do so in schematic.

    I can't recognize in your crazy layout (pls. excuse this expression: it seems not clearly arranged, but correct) if your power supply connections are also substrate/well taps, but if so, they are far too far away from their MOSFETs, I think.



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  3. #3
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    Re: Calibre PEX simulation results

    Quote Originally Posted by erikl View Post
    If you use Inherited Connections in layout, you should do so in schematic.

    I can't recognize in your crazy layout (pls. excuse this expression: it seems not clearly arranged, but correct) if your power supply connections are also substrate/well taps, but if so, they are far too far away from their MOSFETs, I think.
    yeah the layout was auto generated using the chip assembly router feature. I did that to save time and because I wanted to learn the flow with using this design kit and calibre along with it.

    My VDD pin has M1_NWELL_contact over it and my GND pin has M1_PSUB contact over it. You are saying there might be an issue because they are not close enough to the MOSFETs?

    I need to read up on inherited connections issue you mention. There is something obviously wrong with VDD and GND connections.



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  4. #4
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    Re: Calibre PEX simulation results

    Quote Originally Posted by tenso View Post
    yeah the layout was auto generated using the chip assembly router feature. I did that to save time and because I wanted to learn the flow with using this design kit and calibre along with it.
    Oh, that's why! For a manual layouter it looks terrible, but may be correct anyway.

    Quote Originally Posted by tenso View Post
    My VDD pin has M1_NWELL_contact over it and my GND pin has M1_PSUB contact over it. You are saying there might be an issue because they are not close enough to the MOSFETs?
    DRC would tell you, if not close enough. And the auto place & route tool should know about its necessary max. spacing - i.e. should know the DRC rules.

    Also see dick_freebird's contribution to this topic.



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