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  1. #1
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    problem with floating point ip core xilinx

    Hi
    I am facing problem with floating point 5.0v core generator.
    I want convert float to fix and my configuration is:
    floating-point precision : single (32bit)
    fix-point precision :int32(32bit)
    my code is:
    HTML Code:
    module top(x);
    reg clk;
    output [31:0] x;
    real a;
    initial
    	begin
    	clk=1'b0;
    	forever #30 clk=~clk;
    	#600 $stop;
    	end
    initial 
    begin
     a=0.9
    end
      
    	float f2 (
      .a(a), // input [31 : 0] a
      .clk(clk), // input clk
      .result(x) // output [31 : 0] result
    );
    
    endmodule
    INPUT: 0.9
    actual(sim) result:0100000000000000000000000000
    expectative result:00111111011001100110011001100110
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    •   Alt10th March 2018, 18:53

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  2. #2
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    Re: problem with floating point ip core xilinx

    Presume the input number format must be IEEE-754 float rather than real.


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    •   Alt10th March 2018, 19:09

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  3. #3
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    Re: problem with floating point ip core xilinx

    what exist ways for convert real to ieee754?
    for example i have float number=0.9 , how i must to define my float number which i to be able use IEEE754?



    •   Alt10th March 2018, 20:38

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  4. #4
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    Re: problem with floating point ip core xilinx

    Real is an abstract data format only used in simulation and for parameters and constants calculated at synthesis time.
    Conversion function to_float() from real to float is e.g. provided in IEEE float package. I'm not familiar with Xilinx tools and float IP, I don't know if they provide specific conversion functions for constants, but IEEE package should do the trick.


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