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  1. #1
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    Parameterized bitwidth

    Code Verilog - [expand]
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    parameter C_PCI_DATA_WIDTH =128;  
     
    rData <= #1 (rData << 4) - (C_PCI_DATA_WIDTH)'h0014001400140014;    // implements 16*x*x-20 for four different pieces of 32-bit data

    How should we solve the syntax error around (C_PCI_DATA_WIDTH)'h0014001400140014 ??

    •   Alt9th March 2018, 08:37

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  2. #2
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    Re: Parameterized bitwidth

    First, this doesn't look to be parameterized.

    Second, the comment is wrong unless there is a specific set of assumptions on the inputs.

    Third, if such assumptions exist it is much better to write the code in a way the tools can use them.

    for example, this is a 128 bit add (maybe, it looks like you are using 4 16 bit values which is 64b). It isn't clear that this never overflows/underflows into other 32b values.

    I think you want to use for-generate with [32*myGenvar +: 32].



    •   Alt9th March 2018, 09:13

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  3. #3
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    Re: Parameterized bitwidth

    You didn't show the declaration of rData, but you may be able to just write:

    rData <= #1 (rData << 4) - 'h0014001400140014;

    Otherwise you can write
    Code Verilog - [expand]
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    parameter C_PCI_DATA_WIDTH =128;  
    typedef bit [C_PCI_DATA_WIDTH-1:0] PCI_DATA_t;
    rData <= #1 (rData << 4) - PCI_DATA_t'('h0014001400140014);
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation


    1 members found this post helpful.

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